初始化与 c 库 open() 的串行通信导致 TX 在 RPi 上发送一位 [英] Init a serial communication with c library open() causes TX to send one bit on RPi

问题描述

我正在尝试在 RPI 和 FPGA 之间建立串行通信.但是，在使用标准 C 库 open() 初始化串行接口时存在一个问题:我使用示波器来监视通过 RX 和 TX 线路发送和接收的内容.调用 open 会导致 RPI 的 TX 线在一位长度内变低.我在其他计算机/Linux PC 上没有看到这种行为.关键是，FPGA 假定传输有效，因为他认为这是一个起始位，但事实并非如此.

I'm trying to set up a serial communication between the RPI and an FPGA. However, there is an issue when using the standard C library open() to init the serial interface: I'm using a scope to monitor what is sent and received via the RX and TX lines. A call to open causes the TX line of the RPI to go low for the length of one bit. I do not see this behavior with other computers/linux PCs. The point is, the FPGA assumes a valid transmission, since he thinks it's a start bit, but it's not.

我检查了安装在 RPI 上的 minicom.一样.启动 minicom 会导致 TX 线发送一位.minicom 启动后，通信按预期运行，所有字节都具有正确的帧大小.有什么方法可以抑制 TX 线在打开调用以初始化串行通信时变低?这是预期的行为吗?

I checked with minicom installed on the RPI. Same thing. Starting minicom causes the TX line sending one bit. Once minicom has started, the communication runs as expected and all bytes have the correct frame size. Is there any way to suppress the TX line going low upon the open call to init the serial communication? Is this an expected behavior?

推荐答案

这是一个超级牵强的预感，但是 这段代码似乎有点可疑，来自PL011中的pl011_startup()函数串口驱动:

This is a super far-fetched hunch, but this code seems a bit suspicious, from the pl011_startup() function in the PL011 serial port driver:

/*
 * Provoke TX FIFO interrupt into asserting.
 */

它似乎好像在启动端口时在摆弄 TX 线，这可以解释您看到的脉冲.当然，在得出结论之前肯定需要更多的调查.

It seems as if it's twiddling the TX line when starting up the port, which would explain the pulse you're seeing. More investigation would surely be needed before concluding this is what happens, of course.

所以，我想我的答案"归结为:这听起来很奇怪，也许是司机的问题?

So, I guess my "answer" boils down to: that sounds weird, perhaps it's something with the driver?

当然，解决此问题的一种方法是在 FPGA 端小心谨慎，假设您对它有更多控制权.适当的"成帧会解决这个问题，并明确表示可以丢弃虚假发送.

Of course, one way of working around this is to apply some care in the FPGA end, assuming you have more control over it. "Proper" framing would take care of this, and make it clear that the spurious send can be discarded.

更新:我的意思是，如果正确"的消息总是由一些字节序列构成，那么 FPGA 可能无论如何都可以丢弃无效(未成帧")数据，从而变成对随机脉冲免疫.例如，可以将消息定义为始终以 SOH(标题开头)或 SOT(文本开头)符号开头(字节的值分别为 0x01 和 0x02).

UPDATE: I meant that if "proper" messages were to be always framed by some sequence of bytes, the FPGA might be able to discard invalid ("unframed") data anyway, and thus become immune to the random pulse. For instance, messages could be defined to always start with SOH (start of header) or SOT (start of text) symbols (bytes with the values 0x01 and 0x02, respectively).

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