初始化与C库的open（）会导致TX串行通信发送一个位的RPI [英] Init a serial communication with c library open() causes TX to send one bit on RPi

问题描述

我试图建立RPI和FPGA之间的串行通信。但是，使用标准C库时，有一个问题，open（）来初始化串口：我用一个范围来监控通过RX和TX线发送和接收。要打开调用导致RPI的TX线去低一位的长度。我看不出与其他计算机/ Linux的PC这一行为。问题的关键是，在FPGA假定一个有效的传输，因为他认为这是一个起始位，但它不是。

I'm trying to set up a serial communication between the RPI and an FPGA. However, there is an issue when using the standard C library open() to init the serial interface: I'm using a scope to monitor what is sent and received via the RX and TX lines. A call to open causes the TX line of the RPI to go low for the length of one bit. I do not see this behavior with other computers/linux PCs. The point is, the FPGA assumes a valid transmission, since he thinks it's a start bit, but it's not.

我与安装在RPI minicom的检查。同样的事情。启动小型机引起TX线路发送一个位。一旦小型机开始，通信运行正常，所有的字节有正确的帧大小。有什么办法共进晚餐preSS TX线变低时开放调用init串行通信？这是一个预期的行为？

I checked with minicom installed on the RPI. Same thing. Starting minicom causes the TX line sending one bit. Once minicom has started, the communication runs as expected and all bytes have the correct frame size. Is there any way to suppress the TX line going low upon the open call to init the serial communication? Is this an expected behavior?

推荐答案

这是一个超级牵强的预感，但是的这code 似乎有点可疑，从 pl011_startup（）在PL011 串口驱动功能：

This is a super far-fetched hunch, but this code seems a bit suspicious, from the pl011_startup() function in the PL011 serial port driver:

/*
 * Provoke TX FIFO interrupt into asserting.
 */

它的看起来的，如果它的启动端口，这可以解释你所看到的脉冲时摆弄TX线。肯定会结束，这是发生了什么，当然之前需要更多的调查。

It seems as if it's twiddling the TX line when starting up the port, which would explain the pulse you're seeing. More investigation would surely be needed before concluding this is what happens, of course.

所以，我想我的回答归结为：这听起来不可思议，也许这件事情跟司机

So, I guess my "answer" boils down to: that sounds weird, perhaps it's something with the driver?

当然，解决这个工作的一种方式是在FPGA端应用一些照顾，假设你有过更多的控制权。 正确的取景会照顾到这一点，并明确了虚假的发送可以丢弃。

Of course, one way of working around this is to apply some care in the FPGA end, assuming you have more control over it. "Proper" framing would take care of this, and make it clear that the spurious send can be discarded.

更新：我的意思是，如果适当的消息都被字节的一些序列总是被陷害，在FPGA或许能反正放弃无效（无框）的数据，因而成为免疫的随机脉冲。例如，消息可能被定义为总是以 SOH （头​​开始）或 SOT （文本开始）开始符号（字节分别与值0×01和0×02 ）。

UPDATE: I meant that if "proper" messages were to be always framed by some sequence of bytes, the FPGA might be able to discard invalid ("unframed") data anyway, and thus become immune to the random pulse. For instance, messages could be defined to always start with SOH (start of header) or SOT (start of text) symbols (bytes with the values 0x01 and 0x02, respectively).

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