32 位处理器如何支持 64 位整数? [英] How does a 32 bit processor support 64 bit integers?

问题描述

在 C++ 中，您可以使用通常为 4 个字节的 int.long long 整数通常为 8 个字节.如果 cpu 是 32 位的，那不是将其限制为 32 位数字吗?如果它不支持 64 位，我怎么能使用 long long 整数?alu 可以加更大的整数吗?

In C++, you can use an int which is usually 4 bytes. A long long integer is usually 8 bytes. If the cpu was 32 bit, wouldn't that limit it to 32 bit numbers? How come I can use a long long integer if it doesn't support 64 bits? Can the alu add larger integers or something?

推荐答案

大多数处理器都包含一个进位标志和一个溢出标志，以支持对多字整数的操作.进位标志用于无符号数学，溢出标志用于有符号数学.

Most processors include a carry flag and an overflow flag to support operations on multi-word integers. The carry flag is used for unsigned math, and the overflow flag for signed math.

例如，在 x86 上，您可以添加两个无符号 64 位数字(我们假设它们在 EDX:EAX 和 EBX:ECX 中)，如下所示:

For example, on an x86 you could add two unsigned 64-bit numbers (which we'll assume are in EDX:EAX and EBX:ECX) something like this:

add eax, ecx  ; this does an add, ignoring the carry flag
adc edx, ebx  ; this adds the carry flag along with the numbers
; sum in edx:eax

也可以在 C++ 等高级语言中实现这种东西，但它们支持它的工作要少得多，因此代码通常最终会比用汇编语言编写时慢得多.

It's possible to implement this sort of thing in higher level languages like C++ as well, but they do a lot less to support it, so the code typically ends up substantially slower than when it's written in assembly language.

大多数操作本质上基本上是串行的.当您在二进制级别进行加法时，您需要两个输入位并产生一个结果位和一个进位位.然后在添加下一个最低有效位时将进位位用作输入，以此类推(称为波纹加法器"，因为加法会在整个字中产生波纹").

Most operations are basically serial in nature. When you're doing addition at the binary level, you take two input bits and produce one result bit and one carry bit. The carry bit is then used as an input when adding the next least significant bit, and so on across the word (known as a "ripple adder", because the addition "ripples" across the word).

当特定的加法不产生依赖关系时，有更复杂的方法可以减少一个位和另一个位之间的依赖关系，并且大多数当前的硬件都使用这样的东西.

There are more sophisticated ways to do addition that can reduce that dependency between one bit and another when a particular addition doesn't produce a dependency, and most current hardware uses such things.

然而，在最坏的情况下，将 1 添加到已经是给定字长支持的最大数字将导致从每个位到下一个位生成一个进位，一直到整个字.

In the worst case, however, adding 1 to a number that's already the largest a given word size supports will result in generating a carry from every bit to the next, all the way across the word.

这意味着(至少在某种程度上)CPU 支持的字宽限制了它可以运行的最大时钟速度.如果有人非常想这样做，他们可以构建一个可以处理 1024 位操作数的 CPU.但是，如果他们这样做了，他们将有两个选择:要么以较低的时钟速度运行它，要么花费多个时钟来添加一对操作数.

That means that (to at least some extent) the word width a CPU supports imposes a limit on the maximum clock speed at which it can run. If somebody wanted to badly enough, they could build a CPU that worked with, say, 1024-bit operands. If they did that, however, they'd have two choices: either run it at a lower clock speed, or else take multiple clocks to add a single pair of operands.

还请注意，当您像这样扩展操作数时，您需要更多的存储空间(例如，更大的缓存)来存储尽可能多的操作数，需要更多的门来执行每个单独的操作，等等.

Also note that as you widen operands like that, you need more storage (e.g., larger cache) to store as many operands, more gates to carry out each individual operation, and so on.

因此，如果采用相同的技术，您可以拥有一个运行频率为 4 GHz 并具有例如 4 MB 缓存的 64 位处理器，或者运行频率约为 250 MHz 并且可能具有 2 MB 缓存的 1024 位处理器缓存.

So given identical technology, you could have a 64-bit processor that ran at 4 GHz and had, say, 4 megabytes of cache, or a 1024-bit processor that ran at about 250 MHz and had, perhaps, 2 megabytes of cache.

如果您的大部分工作都是在 1024 位(或更大)的操作数上完成的，那么后者可能会是一个胜利.大多数人根本不经常对 1024 位操作数进行数学运算.事实上，64 位数字对于大多数用途来说已经足够大了.因此，在大多数情况下，支持更广泛的操作数可能会成为大多数人的净损失.

The latter would probably be a win if most of your work was on 1024-bit (or larger) operands. Most people don't do math on 1024-bit operands very often at all though. In fact, 64-bit numbers are large enough for most purposes. As such, supporting wider operands would probably turn out to be a net loss for most people most of the time.

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