86 32位运算codeS，在x86的64位不同或者完全删除 [英] x86 32 bit opcodes that differ in x86-x64 or entirely removed

问题描述

我抬头一看维基百科在x86的64位x86的向后兼容性和它说：

I've looked up Wikipedia for x86 backward compatibility in x86-x64 and it says:

x86-64的是完全的16位和32位的x86向后兼容
  code.Because全86的16位和32位指令集留
  在硬件中实现没有任何插入仿真，现有
  86可执行文件没有兼容性或性能运行
  处罚，而那些重codeD现有的应用程序取
  优势的处理器设计的新功能，可以达到
  性能改进。

x86-64 is fully backwards compatible with 16-bit and 32-bit x86 code.Because the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, existing x86 executables run with no compatibility or performance penalties,whereas existing applications that are recoded to take advantage of new features of the processor design may achieve performance improvements.

所以，我测试了一些说明，看到一些实际上是产生完全不同的运算codeS（而不是仅仅将preFIX）如：INC /十二月
综观（86）：

So I've tested some instructions to see that some are actually yield entirely different opcodes (rather than just applying prefix) such as: INC/DEC. Looking at (x86):

\\ X40 INC EAX结果
  \\ X48月EAX

\x40 inc eax
\x48 dec eax

和组装，而同样在86-64的产量：

And while assembling the same in x86-x64 yields:

\\ XFF \\ XC0 INC EAX

\xff \xc0 inc eax

\\ XFF \\ xc8月EAX

\xff \xc8 dec eax

我想弄清楚的原因，那有产生不同的运算codeS相同的症状的其他指令的例子。
我很熟悉PUSH，POP，CALL，RET，进入和离开不可用在x86的64位的32位。

I'm trying to figure out the reason and more examples of other instructions that has the same symptoms that yield different opcodes. I am familiar with that push, pop, call, ret, enter and leave are not available 32 bit in x86-x64.

推荐答案

这是完全删除指令只有真的很晦涩过时的，如二进制和codeD-小数的东西，AAM（乘之后ASCII调整）为做正常的二进制加/子/ MUL / DIV后固定了二进制和codeD-小数。

The only instructions that were entirely removed were really obscure obsolete ones, like binary-coded-decimal stuff and AAM (ascii-adjust after multiplication) for fixing up binary-coded-decimal after doing normal binary add/sub/mul/div.

然而，说明一些编码被删除：在你的情况，32位可以使用 INC R32 单字节操作codeS（0X40 +注册号码） 。 64位模式不仅具有 INC R / M32 编码，其中有第2个字节被指定为递增的寄存器。 （在这种情况下，该0x4x字节被重新利用为REX preFIX字节）。

However, some encodings of instructions were removed: In your case, 32bit can use the inc r32 single-byte opcodes (0x40 + register-number). 64bit mode only has the inc r/m32 encoding, where the register to be incremented is specified with a 2nd byte. (In this case, the 0x4x bytes were repurposed as the REX prefix byte).

英特尔的insn引用（按照 http://stackoverflow.com/tags/x86/info 的链接）显示以下 INC ：

Intel's insn reference (follow the link in http://stackoverflow.com/tags/x86/info) shows the following for inc:

Opcode   Instruction Op/   64-Bit   Compat/
                     En     Mode    Leg mode


FF /0   INC r/m32     M     Valid     Valid      Increment r/m doubleword by 1.

40+ rd  INC r32       O      N.E.     Valid      Increment doubleword register by 1.

N.E。意味着不可编码。

N.E. means not encodable.

在OP / EN栏描述操作数是如何连接codeD。

The Op/En column describes how operands are encoded.

扬Hubicka的 AMD64 ISA概述简要介绍单的再利用 - 字节/减运算codeS为REX prefixes，默认的操作数大小和数据如何直接还是32位。 movabs 可用于装载64位立即数，或加载/存储自/至64位绝对地址。

Jan Hubicka's AMD64 ISA overview briefly describes the repurposing of single-byte inc/dec opcodes for REX prefixes, and the default operand sizes and how immediate data is still 32bit. movabs is available for loading 64bit immediate constants, or load/store from/to a 64bit absolute address.

AMD的AMD64手动，<强>第2.5.11重分配运算codeS 有一个表，是相当短。它仅列出：

AMD's AMD64 manual, Section 2.5.11 Reassigned Opcodes has a table which is quite short. It only lists:

• 4倍INC / DEC R32 即变成REX prefixes


• 63 ARPL ，成为 MOVSXD （符号扩展到DWORD四字，与REX.W = 1时使用（这意味着在REX preFIX = 1 W位））。

• 4x inc/dec r32 that turned into REX prefixes
• 63 ARPL that became MOVSXD (sign-extend dword to qword, when used with REX.W=1 (which means the W bit in the REX prefix = 1)).

早期AMD64和Intel EMT64处理器在长模式冷落 SAHF / LAHF ，但后来重新添加同一运code为32位的指令。该表还没有列出被完全删除指令（BCD指令或者其他人），该被拆除以腾出空间给未来可能的扩展。

Early AMD64 and Intel EMT64 CPUs left out SAHF/LAHF in long mode, but later re-added that instruction with the same opcode as in 32bit. That table also doesn't list instructions that were removed entirely (the BCD instructions and maybe others) that were removed to make room for possible future extensions.

他们可能已经简化了很多东西，并提出X86-64一个更好的清洁与指导更多的空间为将来的扩展，但将从32位系统，任何差异意味着更多的去codeR晶体管。有迹象表明，搬到了64位不同的运算code无机器指令。

They could have simplified things a lot, and made x86-64 a much better cleaner instruction set with more room for future extensions, but every difference from 32bit means more decoder transistors. There are no machine instructions that moved to a different opcode in 64bit.

多机器指令常常共享相同的ASM助记符， MOV 是最重载之一。有加载，存储，MOV立即常数，移动/从段寄存器，都在8位和32位。 （16位是与操作数大小preFIX 32位，同为一个REX preFIX 64位。）有一个sepecial运code从64位绝对地址加载RAX。还有一个特殊的运算code用于加载64位的立即数常量到寄存器中。 （AT＆amp; T公司的语法调用这个movabs，但它仍然是英特尔/ NASM只是MOV）

Multiple machine instructions often share the same asm mnemonic, mov being the most overloaded one. There are loads, stores, mov with immediate-constants, move to/from segment registers, all in 8bit and 32bit. (16bit is the 32bit with an operand-size prefix, same for 64bit with a REX prefix.) There's a sepecial opcode for loading RAX from a 64bit absolute address. There's also a special opcode for loading a 64bit immediate-constant into a register. (AT&T syntax calls this movabs, but it's still just mov in Intel/NASM)

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