同步VS异步复位在FPGA系统 [英] Synchronous vs Asynchronous Resets in FPGA system
问题描述
我是新来使用各种不同的模块，并全部采用同步复位创建FPGA系统来驱动I2C总线（虽然我想，这个问题适用于任何FPGA系统）。
的模块使用一个时钟分频器模块，是以系统时钟，并输出一个低频率到系统的其余部分提供时钟。
我遇到的问题是，当复位信号变低，时钟分频器复位，因此时钟其他模块依赖于停止 - 因此其他模块不注册重置
这是显而易见的解决办法是有一个异步复位，但是，在的赛灵思ISE它似乎并不喜欢他们，并抛出一个警告，说这是利用Spartan-6 FPGA（特别是当code不兼容之后异步code是同步的，这是因为一个I2C总线采用总线时钟把位上车）。
另一种解决方案将是时钟分频器根本就没有被重置，能，因此时钟将永远不会停止，所有的模块会正确地重置。然而，这则意味着该时钟分频器寄存器不能初始化/重新初始化到已知状态 - 我已经被告知将是一个很大的问题，虽然我知道你可以使用：=0/ '1'; 在模拟运营，但这并不实际的FPGA编程一次工作（？）。
什么是同步复位的约定？被时钟发生器通常只是不重？或者他们只是重置的复位信号的瞬时边缘？或者没有我的建议真正解决！
我已经投入了时序图，以及我的code来说明这两个我的意思，并表明我一直在使用code。
非常感谢！
大卫
![在这里输入的形象描述](\"http://i.stack.imgur.com/5Hyus.png\")
库IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.NUMERIC_STD.ALL;
库UNISIM;
使用UNISIM.VComponents.all;
实体CLK_DIVIDER IS
GENERIC（INPUT_FREQ：整数;
OUT1_FREQ：整数;
OUT2_FREQ：INTEGER
）;
PORT（SYSCLK：IN STD_LOGIC;
RESET_N：IN STD_LOGIC;
OUT1：OUT STD_LOGIC;
OUT2：OUT STD_LOGIC）;
END CLK_DIVIDER;
Clk_Divider的建筑行为是
恒divider1：整数：= INPUT_FREQ / OUT1_FREQ / 2;
恒DIVIDER2：整数：= INPUT_FREQ / OUT2_FREQ / 2;
信号计数器1：整数：= 0;
信号计数器2：整数：= 0;
信号输出1：STD_LOGIC：='0';
信号输出2：STD_LOGIC：='0';
开始
output1_proc：过程（SYSCLK）
开始
如果rising_edge（SYSCLK），然后
如果RESET_N ='0'，
计数器1＆下; = 0;
输出1＆所述; ='1';
其他
如果计数器1＆GT; = divider1 - 1，那么
输出1＆LT; =不输出1;
计数器1＆下; = 0;
其他
C1的＆LT; =计数器1 + 1;
万一;
万一;
万一;
结束进程;
output2_proc：过程（SYSCLK）
开始
如果rising_edge（SYSCLK），然后
如果RESET_N ='0'，
计数器2＆下; = 0;
输出2＆所述; ='1';
其他
如果C2的＆GT; = DIVIDER2 - 1，那么
输出2＆LT; =不输出2;
计数器2＆下; = 0;
其他
C2的＆LT; = C2的+ 1;
万一;
万一;
万一;
结束进程;
OUT1＆LT; =输出1;
OUT2＆LT; =输出2;
最终行为;
不产生与用户逻辑内部时钟，但使用一个特定设备的PLL / DCM如果确实需要多个时钟。所有的衍生时钟运行的用户逻辑应该再复位被保持，直到时钟稳定，重置用户逻辑所要求的设计可以被释放。是同步复位或异步复位都可以使用。
但我这种情况下，很可能产生一个时钟使能信号代替，并且断言这为一个周期的信号的每次更新都需要为了产生的任何协议，需要使能信号，例如I2C协议以适当时机。
使用较少的时钟，与同步时钟相结合使能信号，使设置为静态时序分析（STA）更容易，同时也避免与复位同步和跨时钟域（CDC）问题。
I'm new to creating a FPGA system to drive an I2C Bus (although I imagine that this problem applies to any FPGA system) using a variety of different modules, and which all use a synchronous reset.
The modules are clocked using a clock divider module that takes the system clock and outputs a lower frequency to the rest of the system.
The problem I'm having is, when the reset signal goes low, the clock divider resets, and therefore the clock that other modules depend on stop - thus the other modules do not register the reset
An obvious solution would be to have an asynchronous reset, however, in Xilinx ISE it doesn't appear to like them and throws a warning saying that this is incompatible with the Spartan-6 FPGA (especially when the code after the asynchronous code IS synchronous, which it is because an I2C bus uses the bus clock to put bits onto the bus).
Another solution would be for the clock divider to simply not be reset-able, thus the clock would never stop and all modules would reset correctly. However this then means that the clock divider registers cannot be initialised/reinitialised to a known state - which I've been told would be a big problem, although I know you can use the := '0'/'1'; operator in simulation, but this does not work once programmed on the actual FPGA(?).
What is the convention for synchronous resets? Are clock generators generally just not reset? Or do they only reset on the instantaneous edge of the reset signal? Or are none of my suggestions a real solution!
I've put in a timing diagram as well as my code to illustrate both what I mean, and to show the code I've been using.
Thanks very much!
David
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY CLK_DIVIDER IS
GENERIC(INPUT_FREQ : INTEGER;
OUT1_FREQ : INTEGER;
OUT2_FREQ : INTEGER
);
PORT(SYSCLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
OUT1 : OUT STD_LOGIC;
OUT2 : OUT STD_LOGIC);
END CLK_DIVIDER;
architecture Behavioral of Clk_Divider is
constant divider1 : integer := INPUT_FREQ / OUT1_FREQ / 2;
constant divider2 : integer := INPUT_FREQ / OUT2_FREQ / 2;
signal counter1 : integer := 0;
signal counter2 : integer := 0;
signal output1 : std_logic := '0';
signal output2 : std_logic := '0';
begin
output1_proc : process(SYSCLK)
begin
if rising_edge(SYSCLK) then
if RESET_N = '0' then
counter1 <= 0;
output1 <= '1';
else
if counter1 >= divider1 - 1 then
output1 <= not output1;
counter1 <= 0;
else
counter1 <= counter1 + 1;
end if;
end if;
end if;
end process;
output2_proc : process(SYSCLK)
begin
if rising_edge(SYSCLK) then
if RESET_N = '0' then
counter2 <= 0;
output2 <= '1';
else
if counter2 >= divider2 - 1 then
output2 <= not output2;
counter2 <= 0;
else
counter2 <= counter2 + 1;
end if;
end if;
end if;
end process;
OUT1 <= output1;
OUT2 <= output2;
end Behavioral;
Don't generate internal clocks with user logic, but use a device specific PLL/DCM if multiple clocks are really needed. All the user logic running on the derived clocks should then be held in reset until the clocks are stable, and reset for user logic can then be released as required by design. Either synchronous reset or asynchronous reset can be used.
But i this case, probably generate a clock enable signal instead, and assert this enable signal for a single cycle each time update of the signals are required in order to generate whatever protocol is needed, e.g. the I2C protocol with appropriate timing.
Using fewer clocks, combined with synchronous clock enable signals, makes setup for Static Timing Analysis (STA) easier, and also avoid issues with reset synchronization and Clock Domain Crossing (CDC).
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