在Makefile文件功能 [英] Functions in Makefile

问题描述

我写一个Makefile中有很多重复性的东西，例如

I am writing a Makefile with a lot of repetitive stuff, e.g.

debug_ifort_Linux:
        if [ $(UNAME) = Linux ]; then                           \
          $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..."  \
                  TARGET=$@ LEXT="ifort_$(UNAME)" -e syst;      \
        else                                                    \
          echo $(err_arch);                                     \
          exit 1;                                               \
        fi

的靶'SYST'被定义，其中，变量'UNAME'被定义（并且通常是Linux的，但也可能由Cygwin的或OSF1）和变量'difort'和'err_arch'也被定义。 code的此块用于很多次不同的编译器目标（使用的名称约定'的 的'）。由于这是一个巨大的冗余code量，我希望能够把它写在一个更简单的方式。例如，我愿做这样的事情：

where the target 'syst' is defined, the variable 'UNAME' is defined (and is usually Linux, but might also by Cygwin or OSF1) and the variables 'difort' and 'err_arch' are also defined. This block of code is used very many times for different compiler targets (using a name convention of ''). Since this is a huge amount of redundant code, I would like to be able to write it in a more simple manner. E.g., I would like to do something like this:

debug_ifort_Linux:
        compile(uname,compiler,flags,petsc_flags,target,lext)

其中编译可能做code根据上述参数的函数。没有人有任何想法我怎么能做到这一点？

where compile could be a function doing the code above based on the arguments. Does anyone have any idea how I could accomplish this?

推荐答案

有3相关的概念：

1. 呼叫函数


2. 多行变量


3. conditionals

1. call function
2. multi-line variables
3. conditionals

重构的结果可能是这样的：

The refactored result could look like this:

ifeq ($(UNAME),Linux)
    compile = $(MAKE) FC=$(1) FFLAGS=$(2) PETSC_FFLAGS=$(3) \
                      TARGET=$@ LEXT="$(1)_$(UNAME)" -e syst
else
    define compile =
        echo $(err_arch)
        exit 1
    endef
endif


debug_ifort:
        $(call compile,ifort,$(difort),"...")

这有一个 \\ 剩下的就是继续为壳 $（MAKE）行。
没有多行变量在这里是必需的，因为它的外壳code的只有一行。
多行变量仅在else块中。

That one \ that is left is to continue the $(MAKE) line for the shell. No multi-line variable is necessary here, because it is just one line of shell code. Multi-line variables are only used in the else block.

如果您不需要参数，你可以使用：=赋值，只是扩大与 $方法（编译）（见的canned~~V食谱的）

If you don't need parameters you can use := assignment and just expand the method with $(compile) (see canned recipes)

注：的使用使前3.82的版本，=不是在为我定义语句的结束认可。我用定义编译代替。

Note: Using make prior to version 3.82, the = was not recognized at the end of the define statement for me. I fixed this by using define compile instead.

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