VHDL微处理器/微控制器 [英] VHDL microprocessor/microcontroller
问题描述
我在Xilinx（VHDL）上学习代码下一步我想要做一个简单的微处理器/微控制器，并在路上学习一些关于切片组件。所以我的目标是尝试使用AMD 2901（4位片）对8位微处理器进行编码。 （我已经有2901的代码和它的输入和输出信号的所有信息）
Im learning to code on Xilinx (VHDL) The next step I want to take is make a simple microprocessor/micro-controller and on the way learn a little about slice components. So my goal is try to code an 8 bits microprocessor using an AMD 2901 (4bits-slice). (I already have the code of the 2901 and all its info about its input and output signals)
我知道第一步将使mP的架构结果是这样的东西（我知道BUS的带宽将是非常不同的寻找）
I know the first step would be make the architecture of the mP so I ended up with something like this (I understand that the bandwidth of the BUS will be very different for what im looking for)
http://www.cs.binghamton.edu/~reckert/wk15fig1.JPG
（基本上所有我知道mP和mControlers我从这里得到它 http：//www.cs.binghamton。 edu /〜reckert / hardwire3new.html ）
这里是准时问题：
-
如何编写一个中央总线，如图所示？/我如何使用一个中央大总线来收听和写我的内存和组件？
How do I code a central Bus like the diagram showed?/how do I make "listen" and "write" my memory and components using a central big BUS like the diagram?
我想使用2901 ALU（其中两个），所以我有一个8位mP。问题是：让我说我的操作码使用 xxxxx001 （其中x是控制信号，001表示为ALU添加）用于ALU上的添加功能，因此... as我有一个切片ALU我的操作码应该 xxxxx001001 给指令的bot ALU？或者ALU应该共享相同的001命令？（我想，可以做到知道如何使用VHDL上的BUS使两个端口听或某事）
I want to use the 2901 ALU (two of them) so I have a 8bit mP. The question is: lets say my opcode is using xxxxx001 (where x are control signals and 001 means add for the ALU) for add function on the ALU, so... as I have a slice ALU my opcode should be xxxxx001001 for give the instruction to bot ALUs? Or ALUs should share the same "001" command?(I guess that can be done knowing how to use a BUS on VHDL making two ports "listen" or something)
如果你可以与我分享一些tuts或链接的信息，可以帮助我的目标，将是真棒，Ive搜索了很多，发现非常少的信息。
If you can share with me some tuts or links with info that can help me with my goal that will be awesome, Ive searched a lot and found very very few info.
推荐答案
这个答案是关于您问题的第三部分。
This answer is about the 3rd part of your question.
您可以查看 MCPU项目。它是一个8位CPU，77行VHDL代码。因为作者将整个设计压缩到32个宏单元中，代码在一些地方有点棘手，但设计文档帮助。
You may find it useful to take a look at the MCPU project. It's an 8-bit CPU in 77 lines of VHDL code. Because the author has squeezed the entire design into 32 macrocells, the code is a little tricky in some places, but the design document helps.
我还创建了一个重构的版本，旨在提高代码可读性，包括下面。注意，我不是该项目的原作者 - 所有的努力都去TimBöscke。
I've also created a refactored version aiming at code readability, which is included below. Note that I'm not the original author of the project -- all kudos go to Tim Böscke.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mcpu is
port (
data_bus: inout std_logic_vector(7 downto 0);
address: out std_logic_vector(5 downto 0);
n_oe: out std_logic;
-- Asynchronous memory interface
n_we: out std_logic;
n_reset: in std_logic;
clock: in std_logic
);
end;
architecture refactored of mcpu is
signal accumulator: std_logic_vector(8 downto 0);
alias carry is accumulator(8);
alias result is accumulator(7 downto 0);
alias opcode is data_bus(7 downto 6);
signal address_register: std_logic_vector(5 downto 0);
signal pc: std_logic_vector(5 downto 0);
signal states: std_logic_vector(2 downto 0);
type cpu_state_type is (FETCH, WRITE, ALU_ADD, ALU_NOR, BRANCH_NOT_TAKEN);
signal cpu_state: cpu_state_type;
type state_encoding_type is array (cpu_state_type) of std_logic_vector(2 downto 0);
constant STATE_ENCODING: state_encoding_type := (
FETCH => "000",
WRITE => "001",
ALU_ADD => "010",
ALU_NOR => "011",
BRANCH_NOT_TAKEN => "101"
);
begin
process (clock, n_reset)
begin
if not n_reset then
-- start execution at memory location 0
address_register <= (others => '0');
states <= "000";
cpu_state <= FETCH;
accumulator <= (others => '0');
pc <= (others => '0');
elsif rising_edge(clock) then
-- PC / Adress path
if cpu_state = FETCH then
pc <= address_register + 1;
address_register <= data_bus(5 downto 0);
else
address_register <= pc;
end if;
-- ALU / Data Path
case cpu_state is
when ALU_ADD =>
accumulator <= ('0' & result) + ('0' & data_bus);
when ALU_NOR =>
result <= result nor data_bus;
when BRANCH_NOT_TAKEN =>
carry <= '0';
when others => null;
end case;
-- State machine
if cpu_state /= FETCH then
cpu_state <= FETCH;
elsif opcode ?= "11" and carry then
cpu_state <= BRANCH_NOT_TAKEN;
else
states <= "0" & not opcode; -- execute instruction
case opcode is
when "00" => cpu_state <= ALU_NOR; -- 011
when "01" => cpu_state <= ALU_ADD; -- 010
when "10" => cpu_state <= WRITE; -- 001
when "11" => cpu_state <= FETCH; -- 000
when others => null;
end case;
end if;
end if;
end process;
-- output
address <= address_register;
data_bus <= result when (cpu_state = WRITE) else (others => 'Z');
-- output enable is active low, asserted only when
-- rst=1, clk=0, and state!=001(wr_acc) and state!=101(read_pc)
n_oe <= '1' when (clock='1' or cpu_state = WRITE or n_reset = '0' or cpu_state = BRANCH_NOT_TAKEN) else '0';
-- write enable is active low, asserted only when
-- rst=1, clk=0, and state=001(wr_acc)
n_we <= '1' when (clock = '1' or cpu_state /= WRITE or n_reset = '0') else '0';
end;
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