哪些Cortex-M3中断可以用于通用工作？ [英] Which Cortex-M3 interrupts can I use for general purpose work?

问题描述

我会有一些代码需要作为特定中断的结果运行。

我不想在上下文中执行它的中断本身，但是我也不希望它在线程模式下执行。

我希望以低于高级别中断的优先级运行它沉淀了它的运行，但也是一个高于线程级别（以及一些其他中断）的优先级。

我想我需要使用其他中断处理程序。 / p>

哪些是最好的使用和最好的方式来调用它们？

我计划使用中断处理程序为我不使用的一些外设，并通过直接通过NVIC设置位来调用它们，但我希望有一个更好的，更正式的方式。

谢谢，

解决方案

ARM Cortex支持一种非常特殊的例外，称为Pen DSV。看来你可以使用这个异常来完成你的工作。几乎所有ARM Cortex的抢占式实时操作系统都使用PendSV来实现上下文切换。

为了使其工作，您需要将PendSV优先级低（将0xFF写入PRI_14寄存器NVIC）。您还应优先考虑PendSV以上的所有IRQ（在NVIC中的各个优先级寄存器中写入较低的数字）。当您准备好处理整个消息时，从高优先级的ISR触发PendSV：

  *（（uint32_t volatile * ）0xE000ED04）= 0x10000000; //触发PendSV 
  

ARM Cortex CPU将完成您的ISR和所有可能被抢占的其他ISR通过它，最终它将拖尾到PendSV异常。这是解析消息的代码应该在哪里。

请注意，PendSV可能被其他ISR抢占。这一切都很好，但是您需要明确地记住通过一个关键的代码段（简单禁用和启用中断）来保护所有共享资源。在ARM Cortex中，通过执行__asm（cpsid i）来禁用中断，并通过__asm（cpsie i）启用中断。 （大多数C编译器为此提供了内置的内在函数或宏。）

I'd have some code that needs to be run as the result of a particular interrupt going off.

I don't want to execute it in the context of the interrupt itself but I also don't want it to execute in thread mode.

I would like to run it at a priority that's lower than the high level interrupt that precipitated its running but also a priority that higher than thread level (and some other interrupts as well).

I think I need to use one of the other interrupt handlers.

Which ones are the best to use and what the best way to invoke them?

At the moment I'm planning on just using the interrupt handlers for some peripherals that I'm not using and invoking them by setting bits directly through the NVIC but I was hoping there's a better, more official way.

Thanks,

解决方案

ARM Cortex supports a very special kind of exception called PendSV. It seems that you could use this exception exactly to do your work. Virtually all preemptive RTOSes for ARM Cortex use PendSV to implement the context switch.

To make it work, you need to prioritize PendSV low (write 0xFF to the PRI_14 register in the NVIC). You should also prioritize all IRQs above the PendSV (write lower numbers in the respective priority registers in the NVIC). When you are ready to process the whole message, trigger the PendSV from the high-priority ISR:

*((uint32_t volatile *)0xE000ED04) = 0x10000000; // trigger PendSV

The ARM Cortex CPU will then finish your ISR and all other ISRs that possibly were preempted by it, and eventually it will tail-chain to the PendSV exception. This is where your code for parsing the message should be.

Please note that PendSV could be preempted by other ISRs. This is all fine, but you need to obviously remember to protect all shared resources by a critical section of code (briefly disabling and enabling interrupts). In ARM Cortex, you disable interrupts by executing __asm("cpsid i") and you enable interrupts by __asm("cpsie i"). (Most C compilers provide built-in intrinsic functions or macros for this purpose.)

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