从OpenCV代码到FPGA代码的转换是否比Matlab代码更容易？ [英] Is conversion from OpenCV code to FPGA code is easier than Matlab code or not?

问题描述

我想做图像处理项目。我想知道我是否想在FPGA上实现这个项目，我应该在第一阶段Matlab或OPEN CV中选择哪个工具？是否可以直接将代码从Open CV转换为FPGA，代码生成器可以直接从Matlab到FPGA使用？

I want to do project on image processing. i want to know if i want to implement this project on FPGA, which tool should I choose at 1st stage Matlab or OPEN CV? and is it possible to convert code from Open CV to FPGA directly like code generator can be used from Matlab to FPGA directly??

推荐答案

首先 - 你为什么要使用FPGA？除非你有充分的理由，否则请避免它！

Firstly - why do you want to use an FPGA? Unless you have to for good reasons, avoid it!

好的理由可能是这样的：

Good reasons can be things like:

• 费用


• 电力


• 尺寸


• 预先存在的硬件必须重新已使用


• 个人兴趣


• 这是一项授权FPGA的任务

• cost
• power
• size
• pre-existing hardware which must be re-used
• personal interest
• it's an assignment where FPGAs are mandated

不好的理由包括图像处理......这必定意味着我需要一个FPGA！

Bad reasons include "image-processing... that must mean I need an FPGA!"

如果你想在FPGA上实现，你需要从一开始就考虑FPGA。与传统处理器相比，它们具有非常特殊的特性，这意味着许多常规算法很难在FPGA上高效实现。传统处理难以实现的其他算法实际上可以在FPGA上完成。

If you want to implement on FPGA you need to think "FPGA" right from the beginning. They have very particular characteristics compared to conventional processors, which means that many "conventional" algorithms are very difficult to implement efficiently on FPGAs. And other algorithms which conventional processing will struggle with can actually be done quite simply on an FPGA.

一个经典（非图像）示例是CRC计算，通常实现在软件中使用查找表，但在FPGA中可以是一个简单的移位寄存器和XOR门。

One classic (non-image) example is CRC calculation, which is often implemented using lookup tables in software, but can be a trivial shift-register and XOR gate in FPGA.

以前有一个Xilinx购买的产品（AccelDSP）可以采用（非常精心制作）Matlab代码并生成VHDL。它表现不佳并被撤回。

There used to be a product which Xilinx bought (AccelDSP) which could take (very carefully crafted) Matlab code and produce VHDL. It didn't do very well and was withdrawn.

Matlab有 HDL-coder ，声称可以完成同样的工作，也可以做Simulink图表。很久以前我对它进行了评估 - 我不知道它现在有多好（虽然它的价格非常昂贵！）。查看网页ti似乎仍然只支持Matlab函数（不是用户定义的对象），这使得它对于存储状态（IMHO）的任何东西都不起作用，因为所有状态必须存储在函数外部，这意味着你有包含所有注册表的in和out struct 。与AccelDSP相同的问题。

Matlab have HDL-coder, which purports to do the same job, as well as doing Simulink diagrams too. I evaluated it quite a long time ago - I don't know how good it is now (although it was eye-wateringly expensive!). Looking at the web page ti still only seems to support Matlab functions (not user defined objects) which makes it a non-starter for anything which stores state in it (IMHO) as all the state must be stored outside the function, meaning you have to have an "in" and "out" struct with all your regs in. Same problem as AccelDSP had.

Xilinx System Generator和Altera的System Builder都使用Simulink作为生成FPGA代码的前端。它们可能非常成功，请注意，您不能只丢弃任意复杂的Simulink模块，并希望生成可合成的FPGA。

Xilinx System Generator and Altera's System Builder both use Simulink as a front-end to producing FPGA code. They can be quite successful, be be aware that you can't just throw arbitrary complex Simulink blocks down and hope to produce a synthsisable FPGA.

再次，您必须思考FPGA从一开始。

Again, you have to think FPGA from the start.

无论使用哪个比较字，我都会比较常规桌面处理器

Wherever a comparative word is used, I am comparing to "conventional desktop processors"

• FPGA内存不足，但它们有很多小块，这意味着它们的总内部带宽可能很大，如果你有足够的小工作要做。内存也是非常低的延迟（单个时钟周期），非常像处理器L1缓存


• 选择（ if..else 类似功能）在FPGA面积方面可能相当昂贵


• 乘法是一种有限的资源，因此当处理器没有时，有时可以使用旧时代的算法MUL指令


• 位宽可以是任意的 - 不需要使用32位元素来表示计算的18位结果。很多时候，这些工具可以为您解决这个问题。

• FPGA's are memory poor but they have lots of small blocks, which means their aggregate internal bandwidth can be enormous, if you have enough small jobs to do. The memory is also very low latency (single clock-cycle), much like a processors L1 cache
• Selections (if..else like functionality) can be quite expensive in terms of FPGA area
• multiplications are a limited resource, so it can sometimes pay to use algorithms from the "olden-days" when processors didn't have MUL instructions
• bit widths can be arbitrary - no need to use 32 bit elements to represent the 18 bit result of a calculation. Much of the time, the tools can figure this out for you.

开发周期也不同。

• 模拟编译和运行相对较快。确保你做了很多这样的事情


• 实际上，合成和布局布线（让你进入可以编程到FPGA芯片中的比特流的操作）会非常长 - 运行。我目前的编译（相对较小）只花了30分钟。你想尽可能避免这样做！

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