Verilog双向握手示例 [英] Verilog two-way handshaking example

问题描述

我正在完成一个项目，要求在处理器内部功能单元之间进行两次握手。我知道它是什么，但是是否有任何标准或简单示例？

I'm finishing up a project and a requirement is two-way handshaking between functional units inside our processor. I know what it is but is there any 'standard' or a good simple example of it?

只有在有数据的情况下，我才可以想到两个单元之间的情况-它们之间的直线，当X发送到Y时，会给出一个单独的已发送信号。当Y收到已接收信号时，将通过另一根导线将其发送给X。一旦X读取了接收到的信号，它将停止在数据线上发送数据，并将已发送的电线设置为0或Z。然后，Y也将接收到的信号也设置为0或Z。

Only thing I can think of between two units, when there's a data-line between them and when X sends to Y, a separate 'sent' signal is given. When Y receives a 'received' signal is sent to X on another wire. Once X reads that received signal it stops sending data on the data-line and sets sent wire to 0 or Z. Y then sets received signal to 0 or Z as well.

这都是同步的（在同一时钟上）。

This is all synchronous (on the same clock).

这是解决此问题的有效方法吗？我认为它在很大程度上可能会变得非常混乱，但我只在基于简单累加器的处理器上工作。

Is this a valid way to go about this? I figure it can get very messy on a large scale but I'm only working on a simple accumulator based processor.

推荐答案

对于单个时钟域，最常见的简单握手是有效/就绪握手。

The most common simple handshake for a single clock domain would be the valid/ready handshake.

如果 X发送到 Y，那么X的输出为 data 和 valid ，Y的输出为 ready 。

If 'X' is sending to 'Y', then X has outputs of data and valid, and Y has an output of ready.

当X有要发送的数据时，它断言有效，并准备就绪。如果有效和就绪在摆锤时钟上处于高电平，则X将考虑要发送的数据，而Y将考虑要接收的数据。

When X has data to send, it asserts valid, and looks at ready. If valid and ready are high on posedge clock, then X will consider the data to be sent, and Y will consider the data to be received.

此方案的优点是您可以在每个时钟周期发送一个数据，而无需停机。如果有效/就绪后的下一个周期的有效值仍然很高，则将其视为第二个数据包。

The advantage of this scheme is that you can send one data per clock cycle without any down time. If valid is still high the next cycle after valid/ready was high, then this is considered a second packet.

此外，也没有要求Y在看到有效值之前先等待它声明准备就绪，Y可以随时声明准备就绪以接收数据。

Also there is no requirement that Y waits to see valid before it asserts ready, Y can assert ready anytime it is available to receive a data.

您描述的方案就是我所说的请求/确认4相握手，因为它需要四个时钟周期来发送一个数据

The scheme you describe is what I would call a 'req/ack 4-phase handshake', in that it takes four clock cycles to send one data

1. req=1 ack=0
2. req=1 ack=1
3. req=0 ack=1
4. req=0 ack=0

这种接口在跨时钟边界执行异步请求时会更好，因为它消除了两次解释数据包的可能性。但是，您不需要完全同步的界面。

This kind of interface would be better when doing an asynchronous request across a clock boundary, as it eliminates any possibility of interpreting a packet twice. But you don't need this for a fully synchronous interface.

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