添加std_logic_vectors时出错 [英] Error adding std_logic_vectors

问题描述

我想要一个添加两个std_logic_vectors的简单模块.但是，使用代码时 下面用+运算符不合成.

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize.

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

我从XST收到的错误消息

The error message I get from XST

第17行+在这种情况下不能有这样的操作数.

Line 17. + can not have such operands in this context.

我想念图书馆吗?如果可能的话，我不想将输入转换为自然数.

Do I miss a library? If possible, I do not wanna convert the inputs into natural numbers.

非常感谢

推荐答案

您希望编译器如何知道std_logic_vector是带符号的还是无符号的?在这两种情况下，加法器的实现都不相同，因此您需要明确告诉编译器您想执行的操作;-)

How do you want the compiler to know if your std_logic_vectors are signed or unsigned ? Adder implementation is not the same in these two cases, so you need to explicitly tell the compiler what you want it to do ;-)

注意:StackOverflow中突出显示VHDL语法很糟糕.将此代码复制/粘贴到您首选的VHDL编辑器中，以便更轻松地阅读.

library IEEE; 
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all; -- don't use this
use IEEE.numeric_std.all; -- use that, it's a better coding guideline

-- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these
-- are the worst libraries ever. They automatically cast all your vectors
-- to signed or unsigned. Talk about maintainability and strong typed language...

entity add_module is
  port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
  );
end add_module;

architecture Behavior of add_module is
begin

  -- Here, you first need to cast your input vectors to signed or unsigned 
  -- (according to your needs). Then, you will be allowed to add them.
  -- The result will be a signed or unsigned vector, so you won't be able
  -- to assign it directly to your output vector. You first need to cast
  -- the result to std_logic_vector.

  -- This is the safest and best way to do a computation in VHDL.

  pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2));

end architecture Behavior;

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