VHDL - ror 和 rol 操作 [英] VHDL - ror and rol operations

问题描述

我该如何解决这个问题?reg 变量定义为:

How can I solve this problem? reg variable is defined as:

 signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";

下面代码中ror操作有问题.错误信息是:

There is a problem with ror operation in the code below. The error message is:

Line 109: Syntax error near "ror".

Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="

--

  process(clk1,up_down,enable,reset)
        begin
        if up_down="1" then
            reg ror 1;
        end if;
        end process;

推荐答案

您的问题是 ror 运算符没有为 std_logic_vector 定义.

Your problem is the the ror operator is not defined for std_logic_vector.

VHDL 表现出一种称为重载的计算机(和硬件描述)语言行为.重载是对不同类型的运算符、函数或过程进行多重定义的地方.编译器在使用运算符(等)(称为签名)时查看类型的组合，并尝试将其与已声明的各种版本进行匹配.这仅在只有一个匹配项时才有效.再多，代码就模糊了，因为编译器不知道要使用哪个版本.任何更少并且没有可供编译器使用的版本.这是您的问题 - 没有使用 std_logic_vector 的 ror 运算符版本.

VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.

您有两种解决方案:

(i) 推荐:使用连接运算符和切片手动实现您的向右旋转行为:

(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:

    if up_down="1" then
        reg <= reg(0) & reg(7 downto 1);
    end if;

(ii) NOT RECOMMENDED : 将您的 std_logic_vector 转换为具有定义的 ror 运算符版本的不同类型，例如 unsigned.为什么不推荐"?因为我永远不建议使用以下任何运算符，因为它们的行为可能会很奇怪(并且它们的行为在不同的 EDA 工具中似乎不一致)；

(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);

ror rol sla sra sll srl

<小时>

顺便说一句，即使为 std_logic_vector 定义了 ror，这一行也是错误的:

---

By the way, this line would be wrong even if ror were defined for std_logic_vector:

reg ror 1;

你不能只说你能说的更多

You can't just say that any more than you could just say

reg + 1;

您需要将两种情况下的操作结果分配给某物.我已经假设你想在这两种情况下将它分配给 reg .

You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.

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