VHDL中的BRAM_INIT [英] BRAM_INIT in VHDL

问题描述

我正在模拟基于处理器的设计，其中程序存储器内容被保存在BRAM中。我正在使用VHDL（推断BRAM）来实现程序存储器。我试图避免CoreGen，因为我想保持设计便携。最终，这种设计将会转到FPGA上。

我正在寻找一种使用VHDL泛型来初始化BRAM内存内容的方法？我知道Coregen使用COE文件来初始化BRAM，但是我们是否有基于VHDL代码的方法来实现？

让我知道你的备用建议。 p>

解决方案

是的，当然有可能。请查看赛灵思综合工具（XST）用户指南 ，具体是第187页。

他们建议这样做的代码转载如下。他们在用户指南中有关于要读取的文件的格式化的注释。请注意，此代码不直接使用泛型，但我可以想像，您可以设置一个常量或通用名称来保存文件名...

   -  
  - 从外部数据文件初始化块RAM 
  -  
库ieee; 
使用ieee.std_logic_1164.all; 
使用ieee.std_logic_unsigned.all; 
使用std.textio.all; 
 
实体rams_20c是
端口（clk：in std_logic; 
我们：std_logic; 
 addr：in std_logic_vector（5 downto 0）; 
 din ：std_logic_vector（31 downto 0）; 
 dout：out std_logic_vector（31 downto 0））; 
 end rams_20c; 
 rams_20c的架构syn是
类型RamType是bit_vector的数组（0到63）（31到0）; 
 impure函数InitRamFromFile（RamFileName：in string）return RamType是
 FILE RamFile：文本在RamFileName中; 
变量RamFileLine：line; 
可变RAM：RamType; 
开始
在RamType'range循环
 readline（RamFile，RamFileLine）; 
 read（RamFileLine，RAM（I））; 
 end loop; 
返回RAM; 
结束函数; 
信号RAM：RamType：= InitRamFromFile（rams_20c.data）; 
 begin 
 process（clk）
 begin 
如果clk'event和clk ='1'则
如果we ='1'则
 RAM（ conv_integer（addr））< = to_bitvector（din）; 
 end if; 
 dout< = to_stdlogicvector（RAM（conv_integer（addr）））; 
 end if; 
结束进程; 
 end syn; 
  

I am simulating a processor based design where the program memory contents are held in a BRAM. I am realizing the program memory using VHDL (inferring BRAMs). I am trying to avoid CoreGen because I want to keep the design portable. Eventually this design will go to an FPGA.

I am looking to see if there is a way to initialize memory contents of the BRAMs using VHDL generics ? I understand that Coregen uses COE file to initialize the BRAM but do we have a VHDL code based way to do this ?

Let me know your alternate suggestions as well.

解决方案

Yes it is certainly possible. Take a look at the Xilinx Synthesis Tool (XST) User guide, specifically page 187.

The code they recommend to do this is reproduced below. They have notes in the user guide regarding the formatting of the file that will be read. Note that this code doesn't directly use generics, but I could imagine that you could possibly set a constant or generic to hold the name of the filename...

--
-- Initializing Block RAM from external data file
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

entity rams_20c is
port(clk : in std_logic;
   we : in std_logic;
   addr : in std_logic_vector(5 downto 0);
   din : in std_logic_vector(31 downto 0);
   dout : out std_logic_vector(31 downto 0));
end rams_20c;
architecture syn of rams_20c is
   type RamType is array(0 to 63) of bit_vector(31 downto 0);
   impure function InitRamFromFile (RamFileName : in string) return RamType is
      FILE RamFile : text is in RamFileName;
      variable RamFileLine : line;
      variable RAM : RamType;
   begin
      for I in RamType’range loop
         readline (RamFile, RamFileLine);
         read (RamFileLine, RAM(I));
      end loop;
      return RAM;
   end function;
signal RAM : RamType := InitRamFromFile("rams_20c.data");
begin
   process (clk)
   begin
      if clk’event and clk = ’1’ then
         if we = ’1’ then
            RAM(conv_integer(addr)) <= to_bitvector(din);
         end if;
         dout <= to_stdlogicvector(RAM(conv_integer(addr)));
      end if;
   end process;
end syn;

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