“零分"在哪里?在Arm Cortex A-9的内核中完成 [英] Where is the "Zero divide" done in kernel for Arm Cortex A-9
问题描述
我正在研究用于零除的内核源代码(2.6.35).
I am looking into kernel source code (2.6.35 ) for Zero divide .
我在用户空间程序中插入了零除,并且所有线程都停止了.
I inserted Zero divide in user space program and all threads stopped.
所以我想知道Arm Cortex A-9的内核中的零除"在哪里?
So I want to know Where is the "Zero divide" done in kernel for Arm Cortex A-9?
我无法为此找到任何陷阱....
I am not able to find any trap for this ....
谢谢
推荐答案
这取决于体系结构.在 x86系统上给定以下用户空间代码:
It depends on the architecture. Given the following user space code on an x86 system:
main() {
int x = 42 / 0;
}
编译器在目标代码中插入一个idivl
命令.当该命令的除数为0执行时,CPU会生成一个除以零的陷阱(类似于中断).这会在内核内部调用divide_error
陷阱处理程序,在x86的情况下,它位于arch/x86/kernel/entry_32.S
中:
the compiler inserts a idivl
command into the object code. When this command is executed with a divisor of 0, the CPU generates a division by zero trap (similar to an interrupt). This calls the divide_error
trap handler inside the kernel, in case of x86 it is located in arch/x86/kernel/entry_32.S
:
ENTRY(divide_error)
RING0_INT_FRAME
pushl_cfi $0 # no error code
pushl_cfi $do_divide_error
jmp error_code
CFI_ENDPROC
END(divide_error)
然后,error_code
目标执行所有必要的操作以处理错误,并最终从陷阱返回.
The error_code
target then takes care of all necessary actions to handle the error and finally returns from the trap.
在 ARM 上,情况有所不同:除少数例外, ARM CPU没有硬件划分指令(例如Arm Cortex A-9没有硬件划分指令).除法需要实现为库功能.对于内核,这是在arch/arm/lib/lib1funcs.S
中实现的,您还可以在其中找到被零处理的除法.对于用户空间应用程序,我想这是作为libgcc库中的库函数实现的.
On ARM, things are different: With a few exceptions, ARM CPUs do not have a hardware division instruction (e.g. Arm Cortex A-9 does not have one). Division needs to be implemented as a library function. For the kernel, this is implemented in arch/arm/lib/lib1funcs.S
where you also find the division by zero handling. For user space applications, I suppose this is implemented as a library function in the libgcc library.
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