在U-Boot开启中断了的ARM Cortex A-9 [英] Enabling Interrupts in U-boot for ARM cortex A-9

问题描述

我想配置一个GPIO中断的uboot的，这样它来测试中断响应时间没有任何干预的操作系统（裸机）。我能够配置引脚多路复用和建立与GPIO引脚中断也是成功的。

I am trying to configure a GPIO interrupt in the uboot, This it to test the Interrupt response time without any OS intervention (Bare-metal). I was able to configure the pin-muxing and also successful in setting up the interrupt with the GPIO pin.

我的问题是关于在中断服务程序的登记。我看到我的平台，中断向量表位于地址0xFFFF0000地址（我读的系统控制寄存器，了解这一点）。中断ID为GPIO为56和，我只是计算在我的中断服务程序应驻留，只是试图与指针我ISR例行写地址的地址。这是做它的正确方法吗？或者我必须采取的所有其他像背景下由我保存等护理？

My question is regarding the registering of the interrupt service routine. I see that the Interrupt vector table for my platform is at address 0xFFFF0000 ( I read the System Control Register to find out this). The interrupt Id for the GPIO was 56 and with that i just calculated the address where my interrupt service routine should reside and just tried writing the address with the pointer to my ISR routine. Is this the right way of doing it? or i have to take care of the all the other things like context saving etc by myself?

请注意：我使用了ARM Cortex A-9

Note : I am using an ARM Cortex A-9.

编辑：

根据我通过code，我有以下问题了答案。定义

Based on the answers i went through the code i have the following questions. The definition of

do_irq为我的架构（ARM V7）没有做多，既然喜欢arch_interrupt_init功能不是为我所定义的CONFIG_USE_IRQ不为我工作。所以，我可以断定中断不支持我的建筑。现在，如果非要定义这个对我自己的，我需要的所有功能实现得到这个工作？由于这是我的凸出一个非常小的一部分，我想看看我能做到这一点，是落实可行的。我只是想知道，如果这需要code的几行字，或需要一些努力来实现这个中断支持。

do_irq for my architecture( arm v7) is not doing much and the CONFIG_USE_IRQ does not work for me since functions like arch_interrupt_init are not defined for me. So i can conclude interrupts are not supported for my architecture. Now If i have to define this on my own what all functions i need to implement to get this working? Since this is a very small part of my proj and i would want to see if i can do this is feasible to implement. I just want to know if this requires few lines of code or requires some effort to implement this interrupt support.

推荐答案

ARM向量所有的中断处理 0xFFFF0018 （或 0x00000018 ）。这通常是无条件的分支的。然后，code将检查一些的中断控制器的硬件来确定数量的 56 。通常情况下，有一个程序来设置中断号的处理程序，所以你不要手动补丁code;这个表是依赖于如何使用的u-boot 中断处理的实现。

The ARM vectors all interrupts to address 0xFFFF0018 (or 0x00000018). This is typically an unconditional branch. Then the code will inspect some interrupt controller hardware to determine the number 56. Typically, there is a routine to set the handler for the interrupt number, so you don't manually patch the code; this table is dependent on how the u-boot interrupt handling is implemented.

在我的的u-boot 源^注意，中断表看起来是这样的，

In my u-boot source^note, the interrupt table looks like this,

.globl _start
_start:
    b       reset
    ldr     pc, _undefined_instruction
    ldr     pc, _software_interrupt
    ldr     pc, _prefetch_abort
    ldr     pc, _data_abort
    ldr     pc, _not_used
    ldr     pc, _irq
    ldr     pc, _fiq
...
_irq:
        .word irq

所以 _irq 是安装中断处理例程的标签;它在同一个文件中的一些汇编，然后调用 do_irq（），根据 CONFIG_USE_IRQ 。该API的一部分是在* lib_arm / interrupts.c *。有些的CPU 被定义为处理程序的的IRQ 的，比如 CPU / ARM720T / interrupts.c 的，对于S3C4510B。在这里，你可以看到，code从该控制器获取一个寄存器，然后跳转到一个表。

So _irq is a label to install a routine for interrupt handling; it does some assembler in the same file and then calls do_irq(), based on CONFIG_USE_IRQ. Part of the API is in *lib_arm/interrupts.c*. Some CPUs are defined to handler irqs, such as cpu/arm720t/interrupts.c, for a S3C4510B. Here you can see that the code gets a register from this controller and then branches to a table.

因此​​，通过默认的的u-boot 似乎不具有的中断支持的。这并不奇怪，因为引导加载器通常是轮询的基于为了简单和速度

So by default u-boot doesn't seem to have support for interrupts. This is not surprising as a boot loader is usually polling based for simplicity and speed.

注意：我的的u-boot 是2009.01，RC3基地

Note: My u-boot is base on 2009.01-rc3.

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