为了处理 arm cortex A9 上的中断，Linux 内核需要多少条指令? [英] How many instructions does Linux kernel need in order to handle an interrupt on an arm cortex A9?
问题描述
我想估计一个 ARM cortex A9 单核处理一个 IRQ 所需的操作码数量.
I would like to estimate the amount of opcodes it takes a ARM cortex A9 single core to handle an IRQ.
假设我使用 Linux 内核 3.4，调用 irq 并执行 irq_handler 需要多少操作码?
Assuming I work with Linux kernel 3.4, how many opcodes it takes to call the irq and execute the irq_handler ?
推荐答案
你的问题是关于如何计算Linux 的中断延迟.至少您可能对中断开始之前需要多长时间感兴趣.我们将在这里忽略 irqs 的这一方面.
You question is related how to calculate the interrupt latency of Linux. At least you might be interested in how long it takes before your interrupt even starts. We will ignore this aspect of irqs here.
一种简单的方法是切换 GPIO 并使用范围来测量中断.您甚至可以多次切换 GPIO 以查看不同阶段所需的时间.此 Window CE 链接 显示了一个测量延迟的示例.一些中断控制器(例如 IMX)具有 I/O 多路复用模式，其中一个中断号将提高/降低特定的 I/O 线.或者，您可以添加代码来切换行(例程见下文).
A simple way is to toggle a GPIO and use a scope to measure the interrupt. You may even toggle the GPIO multiple times to see the time different phases take. This Window CE link shows an example measuring for latency. Some interrupt controller (such as the IMX) have I/O multiplexing modes where an interrupt number will raise/lower a particular I/O line. Alternatively, you can add code to toggle the line (see below for routines).
主要中断处理的来源在 entry-armv.S.为您使用的中断控制器定义了宏，这些宏取决于 .config 文件.例如，有抢占式中断、多中断控制器、SMP 等.primary 向量定义在 entry-armv.S 的底部.一般要点是检查当前操作模式，然后采用 __irq_usr 或 __irq_svc.这些例程有不同的前置码来存储状态，但它们最终都会调用 irq_handler 宏._irq_usr 包含有关 cmpxchg 的内容，但如果您在 .config 中指定 ARM cortex，则此方法不适用.主要区别在于用户模式下发生 IRQ 后可能的上下文切换.你的机器定义了 mach/entry-macro.S 是汇编宏来访问中断控制器并获得一个中断号.然后跳转到通用 irq 处理代码在顶级kernel目录中.
The source for the primary interrupt handling is in entry-armv.S. There are macros defined for the interrupt controller you use and these depend on the .config file. For instance, there is pre-emptive interrupts, multi-interrupt controllers, SMP, etc. The primary vectors are defined at the bottom of entry-armv.S. The general gist is that the current operating mode is inspected and then either __irq_usr or __irq_svc is taken. These routines have a different pre-ample to store state, but they both end up calling the irq_handler macro. The _irq_usr has stuff about cmpxchg, but if you specify and ARM cortex in your .config, this won't apply. The main difference will be the possible context switch after the IRQ occurs in user mode. Your machine defines mach/entry-macro.S which are assembler macros to access the interrupt controller and get an interrupt number. It then jumps to generic irq handling code in the top level kernel directory.
所以第二种方法是检查代码并直接计算.如果您查看源代码，编译内核，然后在 vmlinux 映像上执行 objdump --disassemble 并查找这些符号，这可能会更容易.您将看到 irq_handler 宏展开，它最终应该会跳转到您的 IRQ 代码.
So the second way would be to inspect the code and calculate it directly. This is probably easier if you look at the source, compile your kernel and then do an objdump --disassemble on the vmlinux image and look for these symbols. You will see the irq_handler macro expanded and it should jump to your IRQ code eventually.
从源码可以看出，还有TRACE_IRQFLAGS.您可以通过 make menuconfig(并键入 /TRACE_IRQFLAGS)检查这在您使用的 Cortex A9 上是否可用.不知道有没有.
As you can see from the source, there is also TRACE_IRQFLAGS. You can check to see if this is available on the Cortex A9 you are using with make menuconfig (and type /TRACE_IRQFLAGS). I don't know if it is available or not.
有一些变化，例如，
- 从用户/SVC 模式中断.
- 当前正在运行的其他中断.
- 被中断的代码(例如 stm/ldm)可能需要一些时间才能完成.
- ISR 中的页面错误.至少在某些 Linux 版本中，某些 Alsa 驱动程序可能会出现未分配页面.
- ISR 中的条件.
在示波器上测量将显示 IRQ 服务中的 jitter.检查指令通常会显示 IRQ 可能永远不会被服务；例如，如果更高优先级的中断不断地抢占/阻止 IRQ.可能您需要同时执行这两项操作才能完全优化硬期限.
Measuring on a scope will show the jitter in IRQ servicing. Examining the instructions will generally show that the IRQ may never be serviced; for example if higher priority interrupts constantly pre-empt/prevent the IRQ. Probably you need to do both to fully optimize for a hard deadline.
通常您并不关心整个 IRQ 需要多长时间，而是 IRQ 行被引发和写入/读取某些外围寄存器之间的时间.例如，FIFO 的深度可能有限，如果 IRQ 发生和读取 FIFO 寄存器之间的延迟大于 FIFO_Size x BPS，那么你有 FIFO 溢出的问题.
Often you don't care how long the whole IRQ takes but the time between the IRQ line being raised and writing/reading some peripheral register. For instance, a FIFO may have limited depth and if the latency between the IRQ occurring and reading the FIFO register is greater than FIFO_Size x BPS, then you have issues with the FIFO overflowing.
FIQ 基础结构要快得多，但您可以使用的内核设施要少得多！
The FIQ infra-structure is a lot faster, but the kernel facilities you can use are far less!
Cortex A9 技术参考在附录 B 中有指令计数.大多数 ARM 指令在大多数架构上都是单周期的，除了内存加载/存储、倍数和分支.按照上面的第 3 和第 4 段，找到为您的配置处理 Linux 中断的完整指令路径，然后将其添加；对于估计(如原始问题所问)，您可以只计算指令，因为它们通常是一个周期.
The Cortex A9 technical reference has instruction counts in appendix B. Most ARM instruction are a single cycle on most architectures, except memory load/store, multiples and branches. Follow the 3rd and 4th paragraphs above to find the complete instruction path to handle a Linux interrupt for your configuration and just add it up; for an estimate (as the original question asks) you can just count the instructions as they are generally a single cycle.
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