中断处理的SMP ARM系统上与GIC [英] Interrupt handling on an SMP ARM system with a GIC

问题描述

我想知道的任何设备处理如何中断从点的工作原理是在点点滴滴的中断处理interrupted.I知道，想有明确的端到端中断handing.Let的图片我把整个什么小我知道关于中断处理。

I wanted to know how interrupt handling works from the point any device is interrupted.I know of interrupt handling in bits and pieces and would like to have clear end to end picture of interrupt handing.Let me put across what little I know about interrupt handling.

假设FPGA器件是通过电气线路中断，并获得该FPGA器件的一些数据.Device司机已经有code（中断处理程序），使用功能的request_irq注册。

Suppose an FPGA device is interrupted through electrical lines and get some data .Device driver for this FPGA device already had code (Interrupt handler) registered using request_irq function.

所以，现在的FPGA器件具有一个IRQ线，得到它后打电话到的request_irq，使用该IRQ线路设备发送数据到通用中断控制器和GIC会做许多人的IRQ线一个转换并发送信号给CPU核心，然后调用下面最少code

So now FPGA device have an IRQ line which it get after to call request_irq ,using this IRQ line device send data to the General Interrupt controller and GIC will do many to one translation of IRQ lines and send the signal to CPU core which then call below minimal code

IRQ_handler
SUB       lr, lr, #4       ; modify LR
SRSFD     #0x12!           ; store SPSR and LR to IRQ mode stack
PUSH      {r0-r3, r12}     ; store AAPCS registers on to the IRQ mode stack
BL        IRQ_handler_to_specific_device
POP       {r0-r3, r12}     ; restore registers
RFEFD     sp!              ; and return from the exception using pre-modified LR 

IRQ_handler_to_specific_device什么是我们注册的设备驱动程序使用的request_irq（）调用。

IRQ_handler_to_specific_device is nothing is what we registered in Device driver using request_irq() call.

我还是CPU核心不是如何来了解中断源？（从设备的中断来了）

I still don't how CPU core comes to know about the interrupt source?(from which device interrupt is coming)

还有是什么样的do_irq调用的作用，并共享中断的作品？

Also what is role of call like do_irq and shared interrupts works?

需要一些帮助理解端到端的中断是如何ARM架构的处理图片？

Need some help in understanding end to end picture on how interrupts are handled on ARM architecture?

推荐答案

在 GIC 分为两部分。首先是所谓的在代理商即可。这是全球系统。它具有物理路由到几个中断源;虽然它可能在一个SOC包。第二部分是每个CPU的复制，它叫 CPU接口。在代理商对如何分配的共享外设中断或SPI逻辑。这些都是中断你的问题问的类型。他们的全球硬件中断

The GIC is divided into two sections. The first is called the distributor. This is global to the system. It has several interrupt sources physically routed to it; although it maybe within an SOC package. The second section is replicated per-CPU and it called the cpu interface. The distributor has logic on how to distribute the shared peripheral interrupts or SPI. These are the type of interrupt your question is asking about. They are global hardware interrupts.

在Linux的的范围内，这是在<一个实施href=\"https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-gic.c\"相对=nofollow> IRQ-gic.c 。有一个在<一的一些文件href=\"https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/gic.txt\"相对=nofollow> gic.txt 。其中特别重要的，

In the context of Linux, this is implemented in irq-gic.c. There is some documentation in gic.txt. Of specific interest,

  
• 章：指定GIC寄存器基物理地址（S）和大小。该
    第一个区域是GIC的分销商注册基地和大小。第二区域是
    在GIC的 CPU接口注册基地和大小。

  

• reg : Specifies base physical address(s) and size of the GIC registers. The first region is the GIC distributor register base and size. The 2nd region is the GIC cpu interface register base and size.

在代理商必须在全球范围访问，因此必须小心地管理它的寄存器。在 CPU接口为每个CPU相同的物理地址，但每个CPU有一个单独的实现。分配器可以设置路由的中断特定CPU（包括倍数）。参见：<一href=\"https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-gic.c#n244\"相对=nofollow> gic_set_affinity（）为例。另外，也可以为任何CPU来处理该中断。在 ACK 寄存器将分配IRQ;第一CPU读它时，获取中断。如果多个挂起的IRQ有两种 ACK 来自不同的CPU读取，那么每次都会得到一个不同的中断。第三个CPU的阅读会得到的假的IRQ。

The distributor must be accessed globally, so care must be taken to manage it's registers. The CPU interface has the same physical address for each CPU, but each CPU has a separate implementation. The distributor can be set up to route interrupts to specific CPUs (including multiples). See: gic_set_affinity() for example. It is also possible for any CPU to handle the interrupt. The ACK register will allocate IRQ; the first CPU to read it, gets the interrupt. If multiple IRQs pend and there are two ACK reads from different CPUs, then each will get a different interrupt. A third CPU reading would get a spurious IRQ.

同时，每个CPU接口有一定的私人中断的来源，即用于CPU到CPU中断以及私人计时器等等。但我相信这个问题的重点是物理外围设备（唯一的系统）如何被路由到一个CPU中的SMP系统。

As well, each CPU interface has some private interrupt sources, that are used for CPU-to-CPU interrupts as well as private timers and the like. But I believe the focus of the question is how a physical peripheral (unique to a system) gets routed to a CPU in an SMP system.

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