如何在SMP上处理中断? [英] How are interrupts handled on SMP?

问题描述

如何在SMP(对称多处理器/多核)计算机上处​​理中断?是否只有一个或多个内存管理单元?

How are interrupts handled on SMP (Symmeteric multiprocessor/multicore) machines? Is there only one memory management unit or more?

说两个线程，A和B在不同的内核上运行(同时)接触页面表中不存在的内存页面，在这种情况下将出现页面错误，并从中引入新页面记忆.

Say two threads, A and B running on different cores touch a memory page (at the same time) which is not there in the page table, in which case there will be a page fault and a new page is brought in from the memory.

将要发生的事件顺序是什么?如果有一个内存管理单元，则页面错误将转发到哪个内核?内核如何处理它?是否有多个内核实例，每个实例都运行在不同的内核上?如果是这样，它们如何在诸如页面错误处理之类的事件上进行同步?

What is the sequence of events which will happen? If there is one memory management unit, to which core is the page fault forwarded to? How does the kernel handle it? Are there multiple instances of the kernel, each one running on a different core? If so, how do they synchronize on such events as page fault handling?

推荐答案

在多核/多处理器体系结构上， APIC用于将中断路由到内核/处理器.顾名思义，可以对APIC进行编程以根据需要进行路由.

On multicore/multiprocessor architectures, an APIC is used to route interrupts to cores/processors. As the name implies, APICs can be programmed to do the routing as desired.

关于内核的同步:这取决于内核/OS.您可以使用带锁定的方案(尽管在非高速缓存一致性体系结构上可能需要IPI)，也可以使用建议的在每个内核上运行内核的方法，并使用某种显式的内核间通信.

Regarding the synchronization of the kernel: This depends on the kernel/OS. You can either use a scheme with locking (although IPIs might be necessary on non-cachecoherent architectures) or you can also use your suggested approach of running a kernel on every core and use some kind of explicit inter-kernel communication.

Barrelfish 是运行多个内核的OS的示例.如果您对这种体系结构感兴趣，则可能需要阅读" Multikernel:一种新的OS体系结构.用于可扩展的多核系统"

Barrelfish is an example of an OS running multiple kernels. If you are interested in that kind of architecture, you might want to read the paper "The Multikernel: A new OS architecture for scalable multicore systems"

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