使用 ARM GIC(全局中断控制器)禁用中断 [英] Disabling interrupt with the ARM GIC (global interrupt controller)

问题描述

我有一个特定要求，我需要在特定时间段内禁用我的设备中断而不影响其他中断(在 ARM 处理器上运行的代码).ARM 文档指出ARM 的所有GIC 寄存器(与启用、禁用和清除中断相关)都是Banked 寄存器，即每个CPU 接口有一个.可从指定 CPU 访问的存储寄存器，并仅控制该 CPU 的 PPI 和 SGI 中断.

I have a specific requirement where I nee to disable my device interrupt for specific period without affecting other interrupts(code running on ARM processor). ARM document pointed that all GIC registers (related to enable, disable and clear interrupts) of ARM are Banked registers, that is there is one per CPU Interface. Banked registers accessible from the designated CPU and controls that CPU's PPI and SGI interrupts only.

这是什么意思?如果我通过写入 GIC 寄存器禁用特定中断，那是仅在该内核上禁用还是在所有内核上禁用?

What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?

推荐答案

GIC 有两个寄存器组；每个 CPU 集和 distribution(也是 distributor)，它是 GIC 的系统全局.对于上面的链接，IrqEnSet0 是每个 CPU 的寄存器，它(再次)被存储并处理 CPU 的 PPI 和 SGI 中断.IrqEnSet1 是一个全局中断列表，这些中断可能会被禁用.分发版(也是分发版)还可以将某些中断定位到 CPU.

There are two register sets with the GIC; a banked per CPU set and the distribution (also distributor) which is system global for the GIC. For the link above, the IrqEnSet0 is a per-CPU register which is banked (again) and handles the PPI and SGI interrupts to a CPU. The IrqEnSet1 is a list of global interrupts and these maybe disable. The distribution (also distributor) can also target certain interrupts to a CPU.

ARM 对这些寄存器有许多不同的名称，GIC 的nofollow">不同版本.它们的概念是相同的.有一组寄存器不是按 CPU 存储的，它们控制全局，包括在系统范围内禁用中断.希望读者有足够的能力找到并阅读其 SOC 的特定控制器文档.

ARM has many different names for these registers and different versions of the GIC. The concepts are the same for all of them. There is a set of registers that are not banked per-CPU and these control things globally including disabling the interrupts system wide. Hopefully the reader is competent enough to find and read the specific controller documentation for their SOC.

这是什么意思?如果我通过写入 GIC 寄存器禁用特定中断，那是仅在该内核上禁用还是在所有内核上禁用?

What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?

• PPI - 外设私有中断.例如，SMP 系统中的每 CPU 计时器.
• SGI - 软件产生的中断.在其他系统上也称为 IPI.这允许从一个 CPU 向另一个 CPU 发送信号.(IPI 是处理器间中断).
• PPI - peripheral private interrupt. For example, a per-CPU timer in SMP systems.
• SGI - software generated interrupt. Also known as IPI on other systems. This allows signaling from one CPU to another CPU. (IPI is inter-processor interrupt).

这些中断只对每个 CPU 有意义.但是，以太网、SPI、视频、CAN 总线、i2c、ADC 等硬件通常是系统全局的.

These interrupts only make sense for each and every CPU. However, hardware like Ethernet, SPI, Video, CAN bus, i2c, ADC, etc. are usually system global.

对于分配器寄存器，通常全局中断具有读/写启用/禁用.每个 CPU 的寄存器在分发器中可能是只读，并指示存在中断.另一组寄存器(每个 CPU)是启用/禁用每个 CPU 中断的正常机制.当访问分发服务器时，软件应该有一个互锁(信号量)，因为它对系统是全局的.Alternatively, only an elected or boot CPU would use the distributor.每个 CPU 的寄存器都已存储，因此内核可以执行读取-修改-写入而无需担心竞争条件.

For the distributor registers, usually the global interrupts have a read/write enable/disable. The registers for the per-CPU are probably read-only in the distributor and indicate that the interrupt is present. The other set of registers (per-CPU) are the normal mechanism to enable/disable the interrupt per-CPU. Software should have an inter-lock (semaphore) when accessing the distributor as it is global to the system. Alternatively, only an elected or boot CPU would use the distributor. The per-CPU registers are banked so a core may perform a read-modify-write without worrying about race conditions.

参考:ARM 通用中断控制器 - 架构规范，可能需要注册.

Reference: ARM Generic Interrupt Controller - Architecture Specification, may require registration.

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