如何中断多核ARM CPU工作 [英] How do interrupts work on multicore ARM cpu

问题描述

这个问题已经回答了针对x86但是，我找不到太多关于ARM处理器MP像的Cortex-A9，的Cortex-A15等等...

更重要的是我想知道，如果中断可以对非主cpu的提高没有任何配置等。

我就只与主CPU处理软件的工作，因此我把其余的在WFI状态但是我不知道如何对MP的ARM CPU中断工作，是否有可能在主CPU继续执行$ C $第二个CPU的ç和一个捡起来，并跳转到指令量表和执行code？

BTW这里是code我使用的时候才能低功耗模式

  uint32_t的章;    __asm​​__挥发性（MRC P15，0％0，C0，C0，5：= R（REG））;
    章＆安培; = 0xF的;    如果（章大于0）
        转到旋转;＆LT; code＆剪断GT;旋：
    对于（;;）
        cpu_idle（）; // cpu_idle  - ＆GT; WFI
 

解决方案

短期和实际目的正确答案是不会对二级核心正在执行一些配置，你问什么是不可能的......

中断控制器架构中的http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html

要prepare二次核接收的IPI，您需要：

• 启用GIC发行（一次，对整个系统）


• 启用GIC CPU接口（每个内核）


• 启用的IPI要接收（每个内核）


• 设置每个IPI要接收（每个内核）的优先级


• 确保CPU接口中断优先级屏蔽寄存器（对于每个核心）设定为比你上面设置中断优先级优先级较低（较高的数字）。


• 清除CPSR I位（每个内核）

如果您不打算执行中断服务程序，跳过我位的空地。核心会出来WFI，并继续执行。这通常是你想要的系统引导操作。

This question has already been answered for x86 however, I couldn't find much about ARM MP cpus like Cortex-A9, Cortex-A15 etc...

More importantly i want to know if interrupts can be raised on non-primary cpu without any configuration etc.

I am working on a software which deals only with the primary cpu hence i put the rest in WFI state however I am unaware of how interrupts work on the MP arm cpus, Is it possible that the main cpu continues executing code and one of the secondary cpu picks it up and jumps to the instruction in vector table and execute that code ?

btw here is the code I'm using to put them to low power mode

    uint32_t reg;

    __asm__ volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (reg));
    reg &= 0xF;

    if(reg > 0)
        goto spin;

<code snipped>

spin:
    for(;;)
        cpu_idle(); // cpu_idle -> wfi

解决方案

The short and for practical purposes correct answer is that what you ask for is not possible without some configuration being performed on the secondary cores...

The interrupt controller architecture is described (in quite some detail) in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html

To prepare the secondary cores to receive IPIs, you need to:

• Enable the GIC Distributor (once, for the whole system)
• Enable the GIC CPU interface (for each core)
• Enable the IPIs you want to receive (for each core)
• Set the priorities for each IPI you want to receive (for each core)
• Ensure the CPU interface Interrupt Priority Mask Register (for each core) is set to priority level lower (higher number) than the interrupt priority you set above.
• Clear the CPSR I-bit (for each core)

If you don't intend to implement an interrupt handler, skip the clearing of the I-bit. The core will come out of WFI and continue executing. That is normally what you want for a system boot operation.

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