多核CPU中断 [英] multi-core CPU interrupts
问题描述
多核处理器如何处理中断. 我知道单核处理器如何处理中断. 我也知道不同类型的中断. 我想知道多核处理器如何处理硬件，程序，cpu时间序列和输入/输出中断
How does multi-core processors handle interrupts. I know of how single core processors handle interrupts. I also know of the different types of interrupts. I want to know how multi core processors handle hardware, program, cpu time sequence and input/output interrupt
推荐答案
这应被视为的延续或扩展其他答案.
大多数多处理器支持可编程中断控制器，例如英特尔的APIC.这些是复杂的芯片，由许多组件组成，其中某些组件可能是芯片组的一部分.在引导时，所有I/O中断都传递给核心0(引导处理器).然后，在APIC系统中，操作系统可以为每个中断指定哪个内核应处理该中断.如果指定了多个内核，则意味着由APIC系统决定哪个内核应处理传入的中断请求.这称为中断亲和力.对于操作系统和硬件，已经提出了许多调度算法.一种明显的技术是通过循环调度中断来平衡系统负载.另一种是英特尔的此技术，旨在平衡性能和功能.
Most multiprocessors support programmable interrupt controllers such as Intel's APIC. These are complicated chips that consist of a number components, some of which could be part of the chipset. At boot-time, all I/O interrupts are delivered to core 0 (the bootstrap processor). Then, in an APIC system, the OS can specify for each interrupt which core(s) should handle that interrupt. If more than one core is specified, it means that it's up to the APIC system to decide which of the cores should handle an incoming interrupt request. This is called interrupt affinity. Many scheduling algorithms have been proposed for both the OS and the hardware. One obvious technique is to load-balance the system by scheduling the interrupts in a round-robin fashion. Another is this technique from Intel that attempts to balance performance and power.
在Linux系统上，您可以打开/proc/interrupts来查看每个内核处理了每种类型的中断数量.在具有8个逻辑核心的系统上，该文件的内容可能类似于以下内容:
On a Linux system, you can open /proc/interrupts to see how many interrupts of each type were handled by each core. The contents of that file may look something like this on a system with 8 logical cores:
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 19 0 0 0 0 0 0 0 IR-IO-APIC 2-edge timer
1: 1 1 0 0 0 0 0 0 IR-IO-APIC 1-edge i8042
8: 0 0 1 0 0 0 0 0 IR-IO-APIC 8-edge rtc0
9: 0 0 0 0 1 0 0 2 IR-IO-APIC 9-fasteoi acpi
12: 3 0 0 0 0 0 1 0 IR-IO-APIC 12-edge i8042
16: 84 4187879 7 3 3 14044994 6 5 IR-IO-APIC 16-fasteoi ehci_hcd:usb1
19: 1 0 0 0 6 8 7 0 IR-IO-APIC 19-fasteoi
23: 50 2 0 3 273272 8 1 4 IR-IO-APIC 23-fasteoi ehci_hcd:usb2
24: 0 0 0 0 0 0 0 0 DMAR-MSI 0-edge dmar0
25: 0 0 0 0 0 0 0 0 DMAR-MSI 1-edge dmar1
26: 0 0 0 0 0 0 0 0 IR-PCI-MSI 327680-edge xhci_hcd
27: 11656 381 178 47851679 1170 481 593 104 IR-PCI-MSI 512000-edge 0000:00:1f.2
28: 5 59208205 0 1 3 3 0 1 IR-PCI-MSI 409600-edge eth0
29: 274 8 29 4 15 18 40 64478962 IR-PCI-MSI 32768-edge i915
30: 19 0 0 0 2 2 0 0 IR-PCI-MSI 360448-edge mei_me
31: 96 18 23 11 386 18 40 27 IR-PCI-MSI 442368-edge snd_hda_intel
32: 8 88 17 275 208 301 43 76 IR-PCI-MSI 49152-edge snd_hda_intel
NMI: 4 17 30 17 4 5 17 24 Non-maskable interrupts
LOC: 357688026 372212163 431750501 360923729 188688672 203021824 257050174 203510941 Local timer interrupts
SPU: 0 0 0 0 0 0 0 0 Spurious interrupts
PMI: 4 17 30 17 4 5 17 24 Performance monitoring interrupts
IWI: 2 0 0 0 0 0 0 140 IRQ work interrupts
RTR: 0 0 0 0 0 0 0 0 APIC ICR read retries
RES: 15122413 11566598 15149982 12360156 8538232 12428238 9265882 8192655 Rescheduling interrupts
CAL: 4086842476 4028729722 3961591824 3996615267 4065446828 4033019445 3994553904 4040202886 Function call interrupts
TLB: 2649827127 3201645276 3725606250 3581094963 3028395194 2952606298 3092015503 3024230859 TLB shootdowns
TRM: 169827 169827 169827 169827 169827 169827 169827 169827 Thermal event interrupts
THR: 0 0 0 0 0 0 0 0 Threshold APIC interrupts
DFR: 0 0 0 0 0 0 0 0 Deferred Error APIC interrupts
MCE: 0 0 0 0 0 0 0 0 Machine check exceptions
MCP: 7194 7194 7194 7194 7194 7194 7194 7194 Machine check polls
ERR: 0
MIS: 0
PIN: 0 0 0 0 0 0 0 0 Posted-interrupt notification event
PIW: 0 0 0 0 0 0 0 0 Posted-interrupt wakeup event
第一列指定中断请求(IRQ)编号.可以在列表中找到所有正在使用的IRQ编号.文件/proc/irq/N/smp_affinity包含一个用于指定IRQ N亲和力的值.应根据APIC的当前操作模式来解释该值.
The first column specifies the interrupt request (IRQ) number. All the IRQ numbers that are in use can be found in the list. The file /proc/irq/N/smp_affinity contains a single value that specifies the affinity of IRQ N. This value should be interpreted depending on the current mode of operation of the APIC.
一个逻辑内核可以接收多个I/O和IPI中断.此时，将进行本地中断调度，也可以通过为中断分配优先级来进行配置.
A logical core can receive multiple I/O and IPI interrupts. At that point, local interrupt scheduling takes place, which is also configurable by assigning priorities to interrupts.
其他可编程中断控制器与此类似.
Other programmable interrupt controllers are similar.
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