ARM的bootloader：中断向量表理解 [英] ARM bootloader: Interrupt Vector Table Understanding

问题描述

的code以下是U形的引导的第一部分以限定中断向量表，我的问题是如何每线将被使用。据我所知，前两行这是出发点和实施的第一个指令：复位，我们定义如下复位。但是，我们什么时候使用下面这些指令？据System.map的，每一个指令有一个固定的地址，所以_fiq是0x0000001C，当我们要执行FIQ，我们将这个地址复制到电脑，然后执行，对不对？但以何种方式，我们才能跳到这个指令：LDR PC，_fiq？它是由硬件或软件来实现？希望我让自己正确理解。

 ＆GT; .globl _start
＆GT; _start：B复位
＆GT; LDR PC，_undefined_instruction
＆GT; LDR PC，_software_interrupt
＆GT; LDR PC，_ prefetch_abort
＆GT; LDR PC，_data_abort
＆GT; LDR PC，_not_used
＆GT; LDR PC，_irq
＆GT; LDR PC，_fiq＆GT; _undefined_instruction：.word undefined_instruction
＆GT; _software_interrupt：.word software_interrupt
＆GT; _ prefetch_abort：.word prefetch_abort
＆GT; _data_abort：.word data_abort
＆GT; _not_used：.word NOT_USED
＆GT; _irq：.word IRQ
＆GT; _fiq：.word FIQ
 

解决方案

如果您了解重置那么你理解他们。

当处理器复位，然后硬件设置PC为0x0000，并开始通过为0x0000取指令执行。当执行或尝试执行​​的硬件未定义的指令作出响应由PC设定为0x0004单元和开始于0x0004单元执行指令。 IRQ中断，硬件完成它正在执行执行地址0x0018处的指令开始的指令。等

  00000000＆LT; _start计算值：
   0：ea00000d b 3C＆LT;被重置GT;
   4：e59ff014 LDR PC，[PC，＃20]; 20℃_undefined_instruction＆GT;
   8：e59ff014 LDR PC，[PC，＃20]; 24 LT; _software_interrupt＆GT;
   C：e59ff014 LDR PC，[PC，＃20]; 28和; _ prefetch_abort＆GT;
  10：e59ff014 LDR PC，[PC，＃20]; 2C＆LT; _data_abort＆GT;
  14：e59ff014 LDR PC，[PC，＃20]; 30℃_not_used＆GT;
  18：e59ff014 LDR PC，[PC，＃20]; 34  - ; _irq＆GT;
  1C：e59ff014 LDR PC，[PC，＃20]; 38 LT; _fiq＆GT;00000020＆所述; _undefined_instruction计算值：
  20：00000000 andeq R0，R0，R000000024＆所述; _software_interrupt计算值：
  24：00000000 andeq R0，R0，R000000028＆LT; _ prefetch_abort计算值：
  28：00000000 andeq R0，R0，R00000002c＆所述; _data_abort计算值：
  2C：00000000 andeq R0，R0，R000000030＆LT; _not_used计算值：
  30：00000000 andeq R0，R0，R000000034＆所述; _irq计算值：
  34：00000000 andeq R0，R0，R000000038＆所述; _fiq计算值：
  38：00000000 andeq R0，R0，R0
 

现在当然除了改变PC和开始从这些地址执行。硬件将节省机器的状态下，如果必要的切换处理器模式，然后开始在从矢量表中的新地址执行

我们的程序员的工作是建立二元使得对于每这些指令来运行我们想要的指令是在正确的地址。硬件提供了一个字，每个位置一个指令。现在，如果你休想曾经有这些例外的，你不必须有一个分公司;例如零地址你可以有你的程序的开始，没有什么神奇的关于这些地址的内存。如果你希望有这些例外，那么你有是一个词，可以跳出下面的异常的方式说明两种选择。一个是分支另一个是负荷件。有优点和缺点每个。

The code following is the first part of u-boot to define interrupt vector table, and my question is how every line will be used. I understand the first 2 lines which is the starting point and the first instruction to implement: reset, and we define reset below. But when will we use these instructions below? According to System.map, every instruction has a fixed address, so _fiq is at 0x0000001C, when we want to execute fiq, we will copy this address into pc and then execute,right? But in which way can we jump to this instruction: ldr pc, _fiq? It's realised by hardware or software? Hope I make myself understood correctly.

>.globl _start  
>_start:b         reset  
>       ldr       pc, _undefined_instruction  
>       ldr       pc, _software_interrupt  
>       ldr       pc, _prefetch_abort  
>       ldr       pc, _data_abort  
>       ldr       pc, _not_used  
>       ldr       pc, _irq  
>       ldr       pc, _fiq  

>_undefined_instruction: .word undefined_instruction  
>_software_interrupt:    .word software_interrupt  
>_prefetch_abort:        .word prefetch_abort  
>_data_abort:            .word data_abort  
>_not_used:              .word not_used  
>_irq:                   .word irq  
>_fiq:                   .word fiq  

解决方案

If you understand reset then you understand all of them.

When the processor is reset then hardware sets the pc to 0x0000 and starts executing by fetching the instruction at 0x0000. When an undefined instruction is executed or tries to be executed the hardware responds by setting the pc to 0x0004 and starts executing the instruction at 0x0004. irq interrupt, the hardware finishes the instruction it is executing starts executing the instruction at address 0x0018. and so on.

00000000 <_start>:
   0:   ea00000d    b   3c <reset>
   4:   e59ff014    ldr pc, [pc, #20]   ; 20 <_undefined_instruction>
   8:   e59ff014    ldr pc, [pc, #20]   ; 24 <_software_interrupt>
   c:   e59ff014    ldr pc, [pc, #20]   ; 28 <_prefetch_abort>
  10:   e59ff014    ldr pc, [pc, #20]   ; 2c <_data_abort>
  14:   e59ff014    ldr pc, [pc, #20]   ; 30 <_not_used>
  18:   e59ff014    ldr pc, [pc, #20]   ; 34 <_irq>
  1c:   e59ff014    ldr pc, [pc, #20]   ; 38 <_fiq>

00000020 <_undefined_instruction>:
  20:   00000000    andeq   r0, r0, r0

00000024 <_software_interrupt>:
  24:   00000000    andeq   r0, r0, r0

00000028 <_prefetch_abort>:
  28:   00000000    andeq   r0, r0, r0

0000002c <_data_abort>:
  2c:   00000000    andeq   r0, r0, r0

00000030 <_not_used>:
  30:   00000000    andeq   r0, r0, r0

00000034 <_irq>:
  34:   00000000    andeq   r0, r0, r0

00000038 <_fiq>:
  38:   00000000    andeq   r0, r0, r0

Now of course in addition to changing the pc and starting execution from these addresses. The hardware will save the state of the machine, switch processor modes if necessary and then start executing at the new address from the vector table.

Our job as programmers is to build the binary such that the instructions we want to be run for each of these instructions is at the right address. The hardware provides one word, one instruction for each location. Now if you never expect to ever have any of these exceptions, you dont have to have a branch at address zero for example you can just have your program start, there is nothing magic about the memory at these addresses. If you expect to have these exceptions, then you have two choices for instructions that are one word and can jump out of the way of the exception that follows. One is a branch the other is a load pc. There are pros and cons to each.

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