大会code对LPC2148 ARM处理器打造的中断向量 [英] Assembly code for creating interrupts vector on LPC2148 ARM processor
问题描述
我最近刚刚开始与LPC2148 ARM处理器的工作。
I have just recently started to work with LPC2148 ARM processor.
我想了解关于建立中断向量的一些汇编code。
I am trying to understand some assembly code regarding the creation of the interrupts vector.
这里是code：
// Runtime Interrupt Vectors
// -------------------------
Vectors:
b _start // reset - _start
ldr pc,_undf // undefined - _undf
ldr pc,_swi // SWI - _swi
ldr pc,_pabt // program abort - _pabt
ldr pc,_dabt // data abort - _dabt
nop // reserved
ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
ldr pc,_fiq // FIQ - _fiq
#if 0
// Use this group for production
_undf: .word _reset // undefined - _reset
_swi: .word _reset // SWI - _reset
_pabt: .word _reset // program abort - _reset
_dabt: .word _reset // data abort - _reset
_irq: .word _reset // IRQ - _reset
_fiq: .word _reset // FIQ - _reset
#else
// Use this group for development
_undf: .word __undf // undefined
_swi: .word __swi // SWI
_pabt: .word __pabt // program abort
_dabt: .word __dabt // data abort
_irq: .word __irq // IRQ
_fiq: .word __fiq // FIQ
__undf: b . // undefined
__swi: b . // SWI
__pabt: b . // program abort
__dabt: b . // data abort
__irq: b . // IRQ
__fiq: b . // FIQ
#endif
.size _boot, . - _boot
.endfunc
我不明白什么是不惜一切怎么回事。
如果有人能向我解释的过程中，特别是如何LDR指令用在这里，我就要AP preciate它。
I dont understand what is going on here at all. If someone could explain to me the process, especially how the ldr instruction is used here, i would appreciate it.
塔尔
推荐答案
我要删除条件code，因为它只是复杂的事情：
I'm going to remove the conditional code, since it just complicates things:
// Runtime Interrupt Vectors
// -------------------------
Vectors:
b _start // reset - _start
ldr pc,_undf // undefined - _undf
ldr pc,_swi // SWI - _swi
ldr pc,_pabt // program abort - _pabt
ldr pc,_dabt // data abort - _dabt
nop // reserved
ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
ldr pc,_fiq // FIQ - _fiq
_undf: .word __undf // undefined
_swi: .word __swi // SWI
_pabt: .word __pabt // program abort
_dabt: .word __dabt // data abort
_irq: .word __irq // IRQ
_fiq: .word __fiq // FIQ
__undf: b . // undefined
__swi: b . // SWI
__pabt: b . // program abort
__dabt: b . // data abort
__irq: b . // IRQ
__fiq: b . // FIQ
.size _boot, . - _boot
.endfunc
让我们先来看一下复位/启动向量：
Lets look first at the reset/start vector:
b _start
这指令是无条件的分支（跳跃）将在code标有_start我没有在摘要中看到。基本上，它会是初始化堆栈和处理器寄存器，也许有些内存区域那么很可能跳转到一个执行批量初始化的C例程大会。
That instruction is an unconditional branch (a jump) to the the code labeled "_start" which I don't see in your snippet. Basically it'll be the assembly that initializes the stack and processor registers, maybe some memory areas then probably jumps to a C routine that performs the bulk of the initialization.
接下来是不确定的载体的ARM会去当执行一个无效的指令（如果我的记忆是正确的）：
Next is the "undefined" vector that the ARM will go to when an invalid instruction is executed (if my memory is right):
ldr pc, _undf
这指令装载 PC 注册地址在_undf符号（以下简称程序计数器或指令指针）。如果我们看一下 _undf 变量，它包含以符号 __ psented undf 地址重新$ P $。因此， LDR PC，_undf 指令将 PC 与 __ undf 的地址 - 跳转到 __ undf：
That instruction loads the pc register (the 'program counter' or instruction pointer) with the address at the "_undf" symbol. If we look at the _undf variable, it contains the address represented by symbol __undf. So the ldr pc, _undf instruction loads pc with __undf's address - jumping to __undf:.
而在 __ undf 我们看到：
__undf: b .
这只是为了同一个地址的一个分支 - 一个无限循环（ 符号表示'这里'或'这个位置。）
That's just a branch to the same address - an infinite loop (the . symbol means 'here' or 'this location').
因此，对于大多数向量（其中遵循相同的技术为未定义矢量），他们就会跳转到小无限循环。你可以在与code这些标签这适合于有问题的矢量代替无限循环，虽然很多项目并没有因为这些载体发射将重新present某种严重的错误。
So for most of these vectors (which follow the same technique as the undefined vector), they'll just jump to little infinite loops. You could replace the infinite loops at those labels with code that's appropriate for the vector in question, though many projects don't because those vectors firing would represent some sort of serious error.
最后，向量槽这是最有趣的是IRQ向量：
Finally, the vector slot that's most interesting is the IRQ vector:
ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
这看起来像处理程序恩智浦设备。
This looks like the handler for an NXP device.
据加载 PC 从一个存储位置这是相对于 PC读取寄存器的值注册。由于ARM架构IRQ向量是的总是的地址0x00000018（我会忽略实现，可以在其他地方的矢量地图或手臂一样的Cortex-M3使用不同的向量模型），因为的指令流水线的使用解决，将由该指令读取将存储单元中的 PC 寄存器的值效应 0xFFFFF030 ，这是该地址的内存映射那么VICVectAddr 寄存器中的向量中断Controller`（VIC）：
It loads the pc register with the value read from a memory location that's relative to the pc register. Since on the ARM architecture the IRQ vector is always at address 0x00000018 (I'm going to ignore implementations that can map the vectors elsewhere or ARMs like the Cortex-M3 that use a different vector model) and because of the instruction pipeline's effect on using the PC register value for addressing, the memory location that will be read by this instruction will be 0xFFFFF030, which is the address of the memory-mapped VICVectAddr register in the 'Vectored Interrupt Controller` (VIC):
'apparent' Pipeline offset in effective
PC value effect the opcode address
------------- ------------ ----------- ----------
0x00000018 + 0x00000008 - 0x0000ff0 == 0xfffff030
此设备寄存器将包含刚发生（当然VIC需要进行正确的初始化，所以它知道该地址）中断的中断处理程序的地址。
This device register will contain the address of the interrupt handler for the interrupt that just occurred (of course the VIC needs to be properly initialized so it knows that address).
所以 LDR PC，[PC，＃ - 量0xFF0]当执行指令，它会加载 PC 注册在中断服务程序为相应的设备的地址（基本上，跳跃到右边中断处理程序）。
So when the ldr pc,[pc,#-0xFF0] instruction executes, it'll load the pc register with the address of the interrupt handler routine for the appropriate device (basically, jumping to the right interrupt handler).
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