禁用中断与ARM GIC（全局中断控制器） [英] Disabling interrupt with the ARM GIC (global interrupt controller)

问题描述

我有，我的东东来禁用特定期间，我的设备的中断，而不会影响其它中断（在ARM处理器上运行code）的特定需求。 ARM文件指出了ARM的所有GIC寄存器（启用，禁用和清除中断相关的）的编组的寄存器，即有每CPU接口之一。编组的寄存器从指定的CPU访问并控制CPU的PPI和SGI只能中断。

I have a specific requirement where I nee to disable my device interrupt for specific period without affecting other interrupts(code running on ARM processor). ARM document pointed that all GIC registers (related to enable, disable and clear interrupts) of ARM are Banked registers, that is there is one per CPU Interface. Banked registers accessible from the designated CPU and controls that CPU's PPI and SGI interrupts only.

这是什么意思？如果我通过写寄存器GIC禁用特定的中断，是否得到仅在核心或所有核心停用？

What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?

推荐答案

有两个寄存器组与GIC;每个CPU集的开户和 < STRONG>分配 （也分销商），这是系统全局的GIC。对于上面的链接，在 IrqEnSet0 是被存入银行（再次）每个CPU寄存器和处理PPI和SGI中断到CPU。在 IrqEnSet1 是全球性中断的列表并且这些也许禁用。在分配（也是分销商）也可以针对特定的中断给CPU。

There are two register sets with the GIC; a banked per CPU set and the distribution (also distributor) which is system global for the GIC. For the link above, the IrqEnSet0 is a per-CPU register which is banked (again) and handles the PPI and SGI interrupts to a CPU. The IrqEnSet1 is a list of global interrupts and these maybe disable. The distribution (also distributor) can also target certain interrupts to a CPU.

ARM对这些寄存器和的不同版本在 GIC 。其概念是为所有这些相同的。有未每个CPU和这些控制东西全局包括宽禁用中断系统编组的一组寄存器。希望读者足够能力找到并阅读特定的控制器文档的SOC。

ARM has many different names for these registers and different versions of the GIC. The concepts are the same for all of them. There is a set of registers that are not banked per-CPU and these control things globally including disabling the interrupts system wide. Hopefully the reader is competent enough to find and read the specific controller documentation for their SOC.

这是什么意思？如果我通过写寄存器GIC禁用特定的中断，是否得到仅在核心或所有核心停用？

What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?

• PPI - 外设私人中断。例如，每个CPU定时器SMP系统。


• SGI - 软件产生的中断。又称IPI在其他系统上。这使得信号从一个CPU到另一个CPU。 （IPI是处理器间中断）。

• PPI - peripheral private interrupt. For example, a per-CPU timer in SMP systems.
• SGI - software generated interrupt. Also known as IPI on other systems. This allows signaling from one CPU to another CPU. (IPI is inter-processor interrupt).

这些中断才有意义为每个CPU。然而，如以太网，SPI，视频，CAN总线，I2C，ADC等硬件通常是系统全局的。

These interrupts only make sense for each and every CPU. However, hardware like Ethernet, SPI, Video, CAN bus, i2c, ADC, etc. are usually system global.

有关在分销商寄存器，通常是全球性的中断都具有读/写启用/禁用。对于寄存器的每个CPU 的可能的只读在经销商和指示中断是present。另一组寄存器（每CPU）的是正常的机制来启用/禁用每个CPU的中断。软件应该有一个跨锁（信号）时，访问在代理商，因为它是全球性的系统。另外，只有的当选的或引导CPU将使用的分销商即可。每个CPU寄存器存入银行这样一个核心可以执行的读 - 修改 - 写的，不用担心竞态条件。

For the distributor registers, usually the global interrupts have a read/write enable/disable. The registers for the per-CPU are probably read-only in the distributor and indicate that the interrupt is present. The other set of registers (per-CPU) are the normal mechanism to enable/disable the interrupt per-CPU. Software should have an inter-lock (semaphore) when accessing the distributor as it is global to the system. Alternatively, only an elected or boot CPU would use the distributor. The per-CPU registers are banked so a core may perform a read-modify-write without worrying about race conditions.

参考： ARM通​​用中断控制器 - 架构规范，可能需要注册

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