在 ARM Linux 上注册多个 Fast 中断源 [英] Registering multiple Fast interrupt sources on ARM Linux

问题描述

我一直在处理 ARM 上的 Linux 中断:

I have been working with the Linux interrupt on ARM:

• request_irq() 可用于注册中断.

• request_irq() can be used to register an interrupt.

在单个中断线上，您可以使用 SHA_SHIRQ 注册多个中断，即正常的 IRQ.

On a single interrupt line you can register multiple interrupts with SHA_SHIRQ, i.e normal IRQ.

• Linux 是否允许在特定中断线上注册多个 SA_INTERRUPT ?
• 也就是说，我们可以为 ARM 快速中断 或 FIQ 注册多个中断处理程序吗?

• On a particular interrupt line does Linux allow to register multiple SA_INTERRUPT ?
• That is can we register multiple interrupt handlers for an ARM fast interrupts or FIQs?

推荐答案

与 IRQ 一样，FIQ 也有一个来自向量表的入口点.您必须根据位/数字检查中断控制器和分支以处理特定的 FIQ.对于FIQ，这往往会否定存储的寄存器，因为两个例程都必须共享它们.可以让一个 FIQ 例程拥有 banked 寄存器，而其他例程明确保存它们.

Like the IRQ, the FIQ has a single point of entry from the vector table. You must inspect the interrupt controller and branch based on a bit/number to handle the specific FIQ. For the FIQ, this tends to negate the banked registers as both routines would have to share them. It is possible to have one FIQ routine own the banked registers and the others explicitly save them.

当前 Linux FIQ 代码 支持 FIQ 处理程序的堆叠，而不是多个同时的 FIQ 源.你的代码可以使用 set_fiq_regs() 来初始化 FIQ 寄存器.您可以分配一个中断控制器基地址，并拥有检查中断源并跳转到适当处理程序的代码.注意:，内核不提供任何通信机制与FIQ.您将不得不编写自己的互锁.我认为 FIFO 实现应该是 FIQ 安全以及其他 lock免费内核模式.

Thecurrent Linux FIQ code supports stacking of FIQ handlers and not multiple simultaneous FIQ sources. Your code can use set_fiq_regs() to initialize FIQ registers. You may assign an interrupt controller base address and have code that inspects the interrupt source and branch to the appropriate handler. Note:, the kernel doesn't provide any communication mechanism with the FIQ. You will have to write your own interlocks. I think that the FIFO implementations should be FIQ safe as well as other lock free kernel patterns.

这是主线代码中的 FIQ 示例.它是一个 IMX SSI 驱动程序.SSI 汇编程序，符号接口，main文件.FIQ 也称为软 DMA.FIQ 延迟非常小，应该允许高服务频率.通常只有一个设备需要这种关注.您可以在处理程序中进行多路分解(分支/函数调用/源编号上的指针).FIQ 通常用汇编程序编写的原因是，如果您使用它，性能 是隐式的.此外，FIQ 通常不会被屏蔽，它会增加系统其余部分的IRQ 延迟.通过在汇编程序中编码来提高速度可减少 IRQ 延迟.

Here is a sample of FIQ in the mainline code. It is an IMX SSI driver. SSI assembler, Symbol interface, main file. FIQ is also known as soft DMA. The FIQ latency is very small and should allow high service frequencies. Usually there is only a single device that needs this attention. You can demultiplex in your handler (branch/function call/pointer on source number). The reason a FIQ is often written in assembler is that performance is implicit if you use this. Also, the FIQ will not normally be masked and it will increase IRQ latency for the rest of the system. Making it faster by coding in assembler reduces the IRQ latency.

另见:FIQ-IRQ 差异

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