在Makefile中使用条件规则 [英] Using conditional rules in a makefile

问题描述

我用伪代码捕获了Makefile的意图，然后指出了我所遇到的问题.我正在寻找在测试环境中对用户更友好的Makefile. Makefile的正确用法是以下之一.

I capture the intent of the Makefile in pseudo code, then indicate the issues I have. I'm looking for a Makefile which is more user friendly in a test environment. The correct usage of the Makefile is one of the below.

    make CATEGORY=parser TEST=basic.
    make ALL

如果用户按如下所示给"JUST"命令，则应打印一条消息"CATEGORYdefined TEST undefined"，反之亦然

If a user gives "JUST" the commands as indicated below, it should print a message saying "CATEGORY defined TEST undefined" and vice-versa

    make CATEGORY=parser
    make TEST=basic

我尝试通过以下方式编写Makefile，但出现错误:

I tried writing the Makefile in following ways, but it errors out:

    help:
        echo"Usage: make CATEGORY=<advanced|basic> TEST=<test-case>
        echo"       make ALL

    ifdef CATEGORY
        ifdef TEST
            CATEGORY_TEST_DEFINED = 1
        else
             echo "TEST not defined"
    else
        echo "CATEGORY not defined"
    endif



    ifeq ($(CATEGORY_TEST_DEFINED), 1)
    $(CATEGORY):
        cd $(PROJ)/$(CATEGORY)
        make -f test.mk $(TEST)
    endif

    ifdef ALL
    $(ALL):
         for i in `ls`
         cd $$(i)
         make all
    endif

我的问题是:

1. Makefile中的规则是否可以选择(使用ifdef选择规则和目标).

1. Whether the rules in a Makefile can be selective (using ifdef to select the rules and targets).

回声不起作用. echo应该可以帮助用户正确使用.

echo doesn't work. echo should help the user with correct usage.

推荐答案

问题是echo属于外壳程序； Make可以在命令中将其传递给Shell，但是Make无法执行它.使用info代替:

The problem is that echo belongs to the shell; Make can pass it to the shell in a command, but Make cannot execute it. Use info instead:

ifdef CATEGORY
$(info CATEGORY defined)
else
$(info CATEGORY undefined)
endif

如果您希望规则是有条件的:

If you want the rules to be conditional:

ifdef CATEGORY
ifdef TEST
$(CATEGORY):
    whatever
else
$(info TEST not defined)
else
$(info CATEGORY not defined)
endif

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