GHDL仿真器不支持vhdl属性而不会出现错误? [英] GHDL simulator doesn't support vhdl attributes without error?
问题描述
我编写了一些vivado RTL，然后将一些vhdl属性添加到实体的端口，以定义Xilinx Vivado工具的接口，如下所示:
I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows:
library ieee;
use ieee.std_logic_1164.all;
entity vivado_rtl_island is
port(
-- Clocks
i_m50_clk :in std_logic;
i_m50_rst :in std_logic;
-- APB Command Inteface
s_paddr :in std_logic_vector(31 downto 0);
s_psel :in std_logic;
s_penable :in std_logic;
s_pwrite :in std_logic;
s_pwdata :in std_logic_vector(31 downto 0);
s_pready :out std_logic;
s_prdata :out std_logic_vector(31 downto 0);
s_pread :out std_logic;
s_pslverr :out std_logic
);
end entity;
architecture rtl of vivado_rtl_island is
-- Define APB Interface for "Vivado IP Integrator"
ATTRIBUTE X_INTERFACE_INFO: STRING;
ATTRIBUTE X_INTERFACE_INFO of s_paddr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PADDR";
ATTRIBUTE X_INTERFACE_INFO of s_psel: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSEL";
ATTRIBUTE X_INTERFACE_INFO of s_penable: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PENABLE";
ATTRIBUTE X_INTERFACE_INFO of s_pwrite: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWRITE";
ATTRIBUTE X_INTERFACE_INFO of s_pwdata: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWDATA";
ATTRIBUTE X_INTERFACE_INFO of s_pready: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PREADY";
ATTRIBUTE X_INTERFACE_INFO of s_prdata: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PRDATA";
ATTRIBUTE X_INTERFACE_INFO of s_pslverr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSLVERR";
begin
end architecture;
我尝试使用GHDL如下编译上述rtl:
There I try to compile the above rtl using GHDL as follows:
$ ghdl -a --std=08 --ieee=synopsys --work=work vivado_rtl_island.vhd
GHDL产生以下错误:
GHDL produces the following error:
vivado_rtl_island.vhd:28:33: no "s_paddr" for attribute specification
vivado_rtl_island.vhd:29:33: no "s_psel" for attribute specification
vivado_rtl_island.vhd:30:33: no "s_penable" for attribute specification
vivado_rtl_island.vhd:31:33: no "s_pwrite" for attribute specification
vivado_rtl_island.vhd:32:33: no "s_pwdata" for attribute specification
vivado_rtl_island.vhd:33:33: no "s_pready" for attribute specification
vivado_rtl_island.vhd:34:33: no "s_prdata" for attribute specification
vivado_rtl_island.vhd:35:33: no "s_pslverr" for attribute specification
但是，当我使用modelsim进行编译时，它不会产生错误.
However, when I compile this with modelsim, it doesn't produce an error.
有人知道如何解决GHDL中的此问题，以便我可以添加这些属性，并且模拟器将忽略它们，而不产生错误吗?
Does anybody know how to work around this problem in GHDL so that I can add these attributes and the simulator will ignore them and not produce and error?
推荐答案
请参阅IEEE Std 1076-2008 7.2属性规范，第9段:
See IEEE Std 1076-2008 7.2 Attribute specification, paragraph 9:
实体声明，架构，配置或包的属性的属性规范应立即出现在该声明的声明部分内.同样，设计单元接口对象的属性的属性规范，子程序，块语句或程序包应立即出现在该设计单元的声明部分内，子程序，块语句或程序包.类似地，设计单元，子程序，块语句或程序包的接口对象的属性的属性规范应立即出现在该设计单元，子程序，块语句或程序包的声明部分内. ...
An attribute specification for an attribute of an entity declaration, an architecture, a configuration, or a package shall appear immediately within the declarative part of that declaration. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. ...
设计单位是实体声明(3.2实体声明)，是主要单位(13.1设计单位).在每个IEEE Std 1076修订版(从-1987到-2008，在5.2属性规范中找到-2008之前)中都存在此语义限制. Modelsim无法编译"您的规范.
The design unit is the entity declaration (3.2 Entity declarations), a primary unit (13.1 Design units). This semantic restriction has been in place in every IEEE Std 1076 revision (-1987 through -2008, prior to -2008 found in 5.2 Attribute specification). Modelsim is wrong to 'compile' your specifications.
Xilinx的Vivado综合历史上利用了Modelsim行为.有趣的是，Vivado不一致地遵循了上面第一个引用的7.2句的语义要求，这在较早的修订版中也可以找到，但在第二个版本中却没有.您可以在实体声明部分的实体上声明属性，而Vivado至少在历史上至少需要在体系结构声明部分的端口上指定属性.
Xilinx's Vivado synthesis historically takes advantage of the Modelsim behavior. What's funny here is Vivado inconsistently adheres to the semantic requirement of the first quoted sentence of 7.2 above which is also found in earlier revisions but not the second. You can declare an attribute on an entity in the entity declarative part while Vivado at least historically required specify attributes on ports in the architecture declarative part.
使用ghdl时，一切不会丢失.在分析过程中可以传递一个命令行参数，以放宽各种规则以匹配Modelsim的行为(第三方工具依赖该行为).
All isn't lost when using ghdl. There's a command line argument that can be passed during analysis to relax various rules to match Modelsim's behavior where relied on by third party tools.
ghdl -a --std=08 --ieee=synopsys -frelaxed-rules --work=work vivado_rtl_island.vhdl
vivado_rtl_island.vhdl:28:33:warning: attribute for port "s_paddr" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:29:33:warning: attribute for port "s_psel" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:30:33:warning: attribute for port "s_penable" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:31:33:warning: attribute for port "s_pwrite" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:32:33:warning: attribute for port "s_pwdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:33:33:warning: attribute for port "s_pready" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:34:33:warning: attribute for port "s_prdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:35:33:warning: attribute for port "s_pslverr" must be specified in the entity [-Wspecs]
您可以添加命令行标志-frelaxed-rules，错误将转换为警告.
You can add the command line flag -frelaxed-rules and the errors will be converted to warnings.
标准版本-2008更改了默认的ghdl行为.您会注意到，未指定--std=08时，默认标准遵从性是--std=93c，其中包括-frelaxed-rules，否则与`--std = 93(-1993)兼容.没有-2008修订版，其中包含宽松的规则.
The default ghdl behavior is changed for standard revision -2008. You'd note that without specifying --std=08 the default standard compliance is --std=93c which includes -frelaxed-rules and is otherwise compatible with `--std=93 (-1993). There isn't a -2008 revision with relaxed rules included.
语义限制背后的原因可能是由于领先的供应商(当时为-1987年)无法在不直接访问端口声明的情况下实现在端口上指定用户属性.尽管该供应商可能不再提供VHDL产品，但限制仍然存在.
The reason behind the semantic restriction would stem from a leading (at the time -1987) vendor not being able to implement specifying a user attribute on a port without having direct access to the port declaration. While that vendor is likely no longer providing VHDL products the restriction remains.
我们发现Modelsim的各种实例都在有效地尝试通过市场份额的影响来操纵标准(它们具有命令行-pendanticerrors参数，将许多警告更改为错误).
We find various instances of of Modelsim effectively trying to steer the standard by market share influence (they have a command line -pendanticerrors argument changing a lot of warnings to errors).
ghdl的开发遵循了自己的领导方式，但严格遵守标准是规范(尽管默认为--std=93c)，命令行参数启用警告而不是错误.
ghdl development follows their lead with the exception that strict compliance with the standard is the norm (--std=93c as a default notwithstanding) with command line arguments enabling warnings instead of errors.
这样做的原因是，实施VHDL的人员倾向于按照标准进行操作，而不是对具有最大市场份额的供应商进行反向工程.
The reasoning for this would be that those implementing VHDL tend to do so from the standard and not by reverse engineering the vendor with the greatest market share.
ghla 文档中的-frelaxed-rules描述可能不完整.可以在 VHDL标准的部分以及其他部分中找到提及
The -frelaxed-rules description may not be complete in ghdl documentation. Mention is found in the sections on VHDL standards as well as other sections.
Xilinx已意识到此问题.毫无疑问，Modelsim知道它们与标准有何不同，并且目前还没有供应商参与VHDL标准的修订过程.
Xilinx has been made aware of the issue. Modelsim undoubtedly knows where they vary from the standard and there currently is no vendor participation in the VHDL standard revision process.
浏览ghdl源代码树ghdl-0.35已于2017年12月14日发布，并且问题525 修复了 2018年2月7日(请参见src/vhdl /sem_specs.adb)，使用-frelaxed-rules将端口属性添加到体系结构声明部分，以提供当前功能，而与--std=08无关(在ghdl-0.36开发周期中).
Looking through the ghdl source tree ghdl-0.35 was released on Dec 14, 2017, and Issue 525 had a fix on Feb 7, 2018 (see src/vhdl/sem_specs.adb) to add port attributes to the architecture declarative part with -frelaxed-rules to provide the present functionality regardless of --std=08 (during the ghdl-0.36 developement cycle).
另请参见问题838 与GHDL不同的端口上的Xilinx Vivado和Modelsim支持属性，在github上，OP寻求第二意见，指出此答案有效.
Also see Issue 838 Xilinx Vivado and Modelsim support attributes on ports differently than GHDL, on github wherein the OP sought a second opinion stating this answer is valid.
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