VHDL 函数需要额外的 LE? [英] VHDL Functions requiring additional LEs?

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问题描述

我正在创建一个包,其中包含类似于以下内容的多个定义

I am creating a package that has multiple definitions similar to the following

    -- Control Register Address Type Declaration
    SUBTYPE ctrl_reg_addr_type IS std_logic_vector( ADDR_BITS-1 DOWNTO 0 );
    -- Control Register Data Type Declaration
    SUBTYPE ctrl_reg_data_type IS std_logic_vector( DATA_BITS-1 DOWNTO 0 );
    -- Control Register Type Declaration
    SUBTYPE ctrl_reg_word_type IS std_logic_vector( CTRL_BITS-1 DOWNTO 0 );

    -- Left/Right Line-In Control Type Declarations
    CONSTANT LINE_IN_VOL_BITS : integer := 5;

    SUBTYPE line_in_volume_type IS natural
    RANGE 0 TO ( 2**LINE_IN_VOL_BITS )-1;

    TYPE line_in_ctrl_type IS RECORD

        -- Left/Right Channel Line Input Volume (4:0)
        -- Registers: LINVOL/RINVOL
        -- 0x1F = +12.0dB
        -- ...  =   1.5dB steps
        -- 0x00 = -34.5dB
        -- 0x17 - 0dB (Default)
        volume : std_logic_vector( LINE_IN_VOL_BITS-1 DOWNTO 0 );
        -- Left/Right Channel Line Input Mute to ADC (7)
        -- Registers: LINMUTE/RINMUTE
        -- 0x1 = Enable Mute
        -- 0x0 = Disable Mute
        mute   : std_logic;
        -- Left/Right Channel Line Input Volume and Mute Load (8)
        -- Registers: LRINBOTH/RLINBOTH
        -- 0x1 = Enable Simultaneous Load of LINVOL/LINMUTE <-> RINVOL/RINMUTE
        -- 0x0 = Disable Simultaneous Load
        both   : std_logic;

    END RECORD line_in_ctrl_type;

我想使用类似于以下的函数来修改记录类型中的字段.

I would like to use functions similar to the following to modify the fields within the record types.

    -- Left/Right Line-In Increase Volume Function Body
    FUNCTION increase_volume( ctrl : line_in_ctrl_type )
    RETURN line_in_ctrl_type IS

        VARIABLE volume : line_in_volume_type := 0;
        VARIABLE tmp    : line_in_ctrl_type;

    BEGIN

        tmp    := ctrl;
        volume := natural( to_integer( unsigned( ctrl.volume ) ) );

        IF ( volume < line_in_volume_type'HIGH ) THEN

            volume     := volume + 1;

            tmp.volume := std_logic_vector(
                              to_unsigned( volume, LINE_IN_VOL_BITS ) );

        END IF;

        RETURN ( tmp );

    END FUNCTION increase_volume;

    -- Left/Right Line-In Increase Volume Function Body
    FUNCTION increase_volume( ctrl : line_in_ctrl_type;
                              step : natural )
    RETURN line_in_ctrl_type IS

        VARIABLE volume : line_in_volume_type := 0;
        VARIABLE tmp    : line_in_ctrl_type;

    BEGIN

        tmp    := ctrl;
        volume := natural( to_integer( unsigned( ctrl.volume ) ) );

        IF ( volume < ( line_in_volume_type'HIGH - step ) ) THEN

            volume     := volume + step;

            tmp.volume := std_logic_vector(
                              to_unsigned( volume, LINE_IN_VOL_BITS ) );

        ELSE

            tmp := increase_volume( tmp );

        END IF;

        RETURN ( tmp );

    END FUNCTION increase_volume;

我的问题是,使用与所示示例类似的函数是否会比明确修改记录值使用更多的 LE.

My questions is, will using functions similar to the examples shown, use more LEs than explicitly modifying record values.

推荐答案

在 VHDL 中使用函数是非常抽象的(VHDL 应该如此).它可以与 RTL 尽可能远.这意味着询问 LE 的 at 中会干扰什么真的很难确定.这主要取决于综合工具以及它们如何挑选逻辑结构.

Using functions in VHDL is very abstract (as VHDL should be). It can be about as far from RTL as you can get. This means asking what will be inteferred in LE's at is really difficult to determine. It mostly depends on the synthesis tools and how they pick out logical constructs.

一个函数的合成更像是一个宏.每次调用它时,您可能最终都会实例化同一逻辑块的另一个实例.你多久打电话一次?

A function is synthesised more like a macro. Each time you call it, you may end up instantiating another instance of the same logical block. How often are you calling it?

为了高效使用 LE,您需要编写重复使用功能块的代码.例如编写一个通用结构读/写引擎并使用它一次,但将输入和输出路由到/到各个地方.

For efficient LE usage you need to write code that re-uses functional blocks. e.g. Write a generic structure read/write engine and use it once, but route the inputs and outputs from/to various places.

如果担心LE的使用,还想用函数的话,建议考虑FPGA够不够大.

If you are worried about LE usage, and still want to use functions, I suggest considering if you have a big enough FPGA.

这篇关于VHDL 函数需要额外的 LE?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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