什么是 PDE 缓存? [英] What is PDE cache?

问题描述

我有以下基于 ARM 的 SoC 规格:

I have the following specifications of an ARM based SoC:

• L1 数据缓存 = 32 KB, 64 B/line, 2-WAY, LRU
• L2 缓存 = 1 MB，64 B/行，16 路
• L1 数据 TLB(用于加载):32 个条目，完全关联
• L2 数据 TLB:512 个条目，4 路
• PDE 缓存:16 个条目(每 1 MB 虚拟空间一个条目)

我想知道 PDE 缓存是什么?我想这与 TLB 类似，但我不确定.

And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure.

回答
似乎 PDE(页面目录条目)是 中间表走缓存确实可以与TLB分开实现.

Answer
It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented separately from TLB.

Cortex-A15 MPCore 处理器实现了专用缓存，将中间级别的转换表条目存储为表遍历的一部分.

The Cortex-A15 MPCore processor implements dedicated caches that store intermediate levels of translation table entries as part of a table walk.

推荐答案

这很有趣.ARM 没有在 Cortex-A15、Cortex-A57 文档以及 ARMv7 和 ARMv8 编程指南中提及此 PDE 缓存的存在.

That's interesting. ARM does not name the existence of this PDE cache in Cortex-A15, Cortex-A57 documentations and ARMv7 and ARMv8 programming guides.

PDE 通常代表页面目录条目，因此这可能是一个专用缓存，用于存储这些条目并在进行地址转换时写入 TTBR 寄存器.

PDE generally stands for Page Directory Entry so this may be a dedicated cache to store these entries and write the TTBR register when doing an address translation.

ARM 有一些中间表遍历缓存"，它们与 ASID 字段(地址空间标识符)和 VMID 字段(虚拟机标识符)相关联，所以看起来 PDE 缓存和中间表遍历缓存是相关的.在文档中，中间表遍历缓存"存储翻译表条目的中间级别......所以这很可能是页面目录条目.

ARM has some "intermediate table walk caches" that are associated with an ASID field (address space identifier) and VMID field (virtual machine identifier) so it seems like PDE cache and intermediate table walk cache are related. In the documentation, "intermediate table walk caches" store intermediate levels of translation table entries ... so this may well be the page directory entries.

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