是否有一个如何从 Chisel3 模块生成 verilog 的简单示例? [英] Is there a simple example of how to generate verilog from Chisel3 module?

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问题描述

我正在寻找在 Verilog 中转换简单 Chisel3 模块的简单方法.

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.

我拿凿子官方网页上给出的Gcd源代码.

I take Gcd source code given on official web page of chisel.

  import chisel3._

  class GCD extends Module {
    val io = IO(new Bundle {
      val a  = Input(UInt(32.W))
      val b  = Input(UInt(32.W))
      val e  = Input(Bool())
      val z  = Output(UInt(32.W))
      val v  = Output(Bool())
    })
    val x = Reg(UInt(32.W))
    val y = Reg(UInt(32.W))
    when (x > y) {
      x := x -% y
    }.otherwise {
      y := y -% x
    }
    when (io.e) {
      x := io.a
      y := io.b
    }
    io.z := x
    io.v := y === 0.U
  }

我找不到如何编写 build.sbt 和类实例化以在 Verilog 中进行转换.

I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.

推荐答案

感谢您对 Chisel 的关注!我们通常鼓励人们使用我们的 chisel-template repo 作为 Chisel3 项目的起点:https:///github.com/ucb-bar/chisel-template

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

如果你想做最简单的事情.创建此 build.sbt 并将其放在项目的根目录中.

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.12.13"

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4"

将上面的GCD源代码放在GCD.scala中,并在文件中添加如下内容:

Put the above GCD source code in GCD.scala and add the following to the file:

import chisel3.stage.ChiselStage

object GCDDriver extends App {
  (new ChiselStage).emitVerilog(new GCD, args)
}

然后您可以通过运行:sbt "runMain GCDDriver" 生成 Verilog.默认输出目录为当前目录.

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory.

你可以通过运行 sbt "runMain GCDDriver --help" 来查看可用的命令行选项例如 --target-dir 会让你改变目标目录

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory

这篇关于是否有一个如何从 Chisel3 模块生成 verilog 的简单示例?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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