Verilog模块中一个周期的奇怪延迟 [英] Strange delay of one cycle in modules in verilog
问题描述
我是Verilog和数字电路的初学者，我对以下代码有疑问.在这段代码中，我制作了一个状态机，该状态机将"reg"中的值保存到verilog中的另一个模块中.我编写此代码只是为了解释我的疑问:
i'm beginner in verilog and digital circuits, and i have one doubt in the code below. In this code i made a state machine that saves values in a "reg" into another module in verilog. I made this code just to explain my doubt:
//STATE MACHINE
module RegTest(clk,enable,reset, readData1_out);
parameter State1 = 0;
parameter State2 = 1;
parameter State3 = 2;
parameter State4 = 3;
parameter State5 = 4;
parameter State6 = 5;
parameter State7 = 6;
parameter State8 = 7;
parameter State9 = 8;
parameter State10 = 9;
parameter Beg = 10;
input clk, enable, reset;
output readData1_out;
wire clk,enable, reset;
reg[5:0] State;
reg writeEn ;
reg [15:0] writeData;
wire [15:0] readData1;
wire writeEn_out = writeEn;
RegFile registrador_component (
.dataIn(writeData),
.dataOut(readData1),
.clock(clk),
.writeEnable(writeEn)
);
defparam
registrador_component.WIDTH = 16;
always @(posedge clk or posedge reset) begin
if (reset)
begin
State = Beg;
end else begin
case (State)
Beg:
begin
State = State1;
end
State1:
begin
writeEn = 1 ;
writeData = 10;
State = State2;
end
State2:
begin
writeEn = 0 ;
State = State3;
end
State3:
begin
writeEn = 1;
writeData = readData1 + 10;
State = State4;
end
State4:
begin
writeEn = 0 ;
State = State5;
end
State5:
begin
writeEn = 1 ;
writeData = readData1 + 10;
State = State6;
end
State6:
begin
writeEn = 0 ;
State = State7;
end
State7:
begin
writeEn = 1 ;
writeData = readData1 + 10;
State = State8;
end
State8:
begin
writeEn = 0 ;
State = State9;
end
endcase
end
end
endmodule
//Example of a register file
module RegFile(clock, writeEnable, dataIn, dataOut);
parameter WIDTH = 16;
input clock, writeEnable;
input [WIDTH-1 : 0] dataIn;
output [WIDTH-1 : 0] dataOut;
wire [WIDTH-1 : 0] dataOut;
reg [WIDTH-1 : 0] wha;
assign dataOut = wha;
always@( posedge clock)
begin
if (writeEnable)
wha = dataIn;
end
endmodule
我的疑问是，为什么我需要等待1个周期才能获取存储在RegFile中的值? 为什么我不能跳过State2?
My doubt is, why do I need to wait 1 cycle to get the value that is stored in RegFile? Why can't I skip the State2 for example?
推荐答案
实际上，您在上面编写的代码中确实有2个时钟周期的延迟.如果您对此进行了模拟将很有帮助，这样您就可以自己看到它，但我将对其进行描述.
You do in fact have 2 clock cycles of delay in the code you wrote above. It would help if you simulated this so you can see it for yourself, but I'll describe it.
在第一个周期，WriteEnable变高.要使该逻辑的其他部分有效，需要1个完整的时钟周期.因此，在第一个时钟周期完成后，WriteEnable将可在其他地方使用.
On the first cycle, WriteEnable goes high. It takes 1 full clock cycle to be valid to other parts of the logic. So after the first clock cycle is done, WriteEnable will be available for use elsewhere.
在第二个周期中，您的regFile模块可以看到" WriteEnable先前变高的事实.然后它将把dataIn放入信号，该信号被传递到dataOut.因此，在第二个时钟周期完成之后，dataOut将可在其他地方使用. (在状态3的第三个时钟周期使用它.)
On the second cycle, your regFile module can "see" the fact that WriteEnable went high previously. It then will put dataIn into wha signal, which gets passed to dataOut. So after the second clock cycle is done, dataOut will be available for use elsewhere. (It gets used on the third clock cycle in State 3).
这就是为什么您需要进入状态2.为什么状态2允许RegFile额外需要1个时钟周期来注册输出数据.
This is why you need to go to state 2. State 2 allows for the 1 extra clock cycle needed for RegFile to register the output data.
时钟周期延迟是一个非常重要的概念，可以理解，因此最好在您还不熟悉它的时候就完全掌握它.
Clock cycle delay is an extremely important concept to understand, so it's good that you're putting in the time when you are still new to fully grasp it.
有关更多信息，请参见此处的本教程，它解释了寄存器和时钟周期延迟，对您很有用. 时钟周期延迟和注册逻辑
For more information see this tutorial here, it explains registers and clock cycle delay and will be useful for you. Clock Cycle Delays and Registered Logic
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