是MESI协议就够了，或者是记忆障碍仍需要？ （英特尔CPU） [英] Is the MESI protocol enough, or are memory barriers still required? (Intel CPUs)

问题描述

我发现其中规定，当字符串（不是的std ::字符串，但组装字符串指令）使用内存屏障是必要的，以prevent他们的英特尔文件由CPU被重新排序。

I found an intel document which states memory barriers are required when string (not std::string, but assembly string instructions) are used, to prevent them being re-ordered by the CPU.

然而，当两个线程（在两个不同的内核）正在访问相同的内存也需要记忆障碍是什么？我脑子里想的情形是，它没有CPU的一个自己的高速缓存行写入此内存和核心写入到存储缓冲区（而不是缓存）。内存屏障是必需的，以刷新存储缓冲区缓存的价值，所以其他核心能够获得这个值？

However, are memory barriers also required when two threads (on two different cores) are accessing the same memory? The scenario I had in mind is where one of the CPUs which doesn't "own" the cache line writes to this memory and the core writes to its store buffer (as opposed to its cache). A memory barrier is required to flush the value from the store buffer to the cache, so the other core can obtain this value?

我不确定是否在英特尔，MESI协议处理呢？

I am unsure whether, on Intel, the MESI protocol handles this?

（我曾尝试（严重）上面的解释是更好的描述在下面的文章，页6-12）：

(what I have tried to (badly) explain above is better-described in the below paper, pages 6-12):

http://www.puppetmastertrading.com/images/hwViewForSwHackers.pdf

以上的纸张很一般，而且我不确定英特尔CPU实际上是如何处理的问题。

The above paper is very general and I am unsure how Intel CPUs practically handle the problem.

推荐答案

MESI协议适用于高速缓存，存储缓冲基本上是pre-缓存，这意味着它是一个还没有被释放到外面的世界商店，它的同步点还没有确定。

MESI protocols apply to caches, store buffering is essentially pre-cache, meaning that it's a store that was not yet "released" to the outside world, and its synchronization point was not yet determined.

您还需要牢记，高速缓存一致性只写入保证不要超高速缓存行的陈旧副本发生，沿途迷路。这些协议的唯一保证是隐藏，你有复制的值（本身就是一个性能优化）高速缓存的事实，并暴露给程序员/ OS单级平板的物理内存的假象。

You also need to keep in mind that cache coherency only guarantees that writes don't occur on stale copies of a cacheline and get lost along the way. The only guarantee of such protocols is to hide the fact that you have caches with copied values (a performance optimization in itself), and expose to the programmer/OS the illusion of a single level flat physical memory.

这，本身给你写的顺序没有保证，并从多个内核中读取，为此你需要使用额外的构造，在ISA提供，如锁，栅栏，依靠管理您的code内存排序规则。

That, by itself, gives you no guarantee on the ordering of writes and reads from multiple cores, for that purpose you need to manage your code using additional constructs that the ISA provides, like locks, fences, and relying on memory ordering rules.

您所描述的情况是不可能的，因为它打破了第一部分 - 即不拥有一条线不能写入内存，因为它会错过，做自己就行了核心更新的数据核心（如果这种存在）。什么是MESI协议下会发生的是，写操作将被缓冲一段时间，而在轮到它时将予发行 - 它会发出所有权的请求，将无效在其他内核该行的所有副本（触发回写，如果有一个修改后的副本），并获取更新的数据。只有这样，作家核心可以修改该行并将其标记为修改。

The situation you describe is not possible as it breaks the first part - a core that does not own a line can't write to memory since it would miss the updated data in the core that does own the line (if such exists). What would happen under a MESI protocol is that the write will be buffered for a while, and when its turn comes to be issued - it would send a request for ownership that would invalidate all copies of that line in other cores (triggering a writeback if there's a modified copy), and fetch the updated data. Only then the writer core may modify the line and mark it as modified.

不过，如果2个核心同时写入同一直线上，MESI协议只能保证这些写会有的部分的秩序，而不是特定的一个你可能想。更糟糕的 - 如果每个内核写几行，你想围绕这些写入原子性，MESI不保证。你需要积极增加一个互斥体或某种形式的障碍，迫使硬件来执行写入你想要的方式。

However, if 2 cores write to the same line simultaneously, MESI protocol only guarantees that these write will have some order, not a specific one you might want. Worse - if each core write several lines and you want atomicity around these writes, MESI doesn't guarantee that. You'll need to actively add a mutex or a barrier of some sort to force the HW to perform the writes the way you want.

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