VHDL - “输入从不使用警告” [英] VHDL - "Input is never used warning"

问题描述

我用VHDL（用于Xilinx Spartan-6）编写了一个程序，在按下按钮时递增计数器，并在按下另一个按钮时将其重置为零。

I've written a program in VHDL (for Xilinx Spartan-6) that increments a counter whilst a button is pressed and resets it to zero when another button is pressed.

但是，我的进程抛出错误警告：Xst：647 - 从不使用输入。这个端口将被保留并保持未连接... 用于重置变量 - 尽管它既用于过程的灵敏度又用作条件（与<$ c $一样多） c>按钮，但不会被标记！）。

However, my process throws the error WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected... for the reset variables - despite the fact that it is used both in the sensitivity of the process and as a condition (just as much as button, yet that doesn't get flagged!).

binary_proc : process(CLK_1Hz, button, reset) --include all inputs on sensitivity list
begin
    if rising_edge(CLK_1Hz) and button = '1' then
        binary <= binary + 1;
    else if reset = '1' then
            binary <= (others => '0');
        end if;
    end if;
end process;

但更奇怪的是，我可以通过简单地使用两个if语句而不仅仅是if-else来解决这个问题if语句，如下所示;

More curiously though, I can fix this by simply using two if statements rather than just an if-else if statement, as shown below;

binary_proc : process(CLK_1Hz, button, reset) --include all inputs on sensitivity list
begin
    if rising_edge(CLK_1Hz) and button = '1' then
        binary <= binary + 1;
    end if;
    if reset = '1' then
        binary <= (others => '0');
    end if;
end process;

我的问题是：当if-else语句出现时，为什么复位变量在电路外优化使用但不使用两个if语句时？造成这种情况的原因是什么，以及如何避免这种情况呢？

My question is: why is the reset variable optimized out of the circuit when an if-else statement is used but not when two if statements are used? What causes this and how can this sort of thing be avoided it?

非常感谢！

注意：该程序的完整代码如下有用！

NB: Full code of the program is below in case it helps!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity button_press is
    port(
        CLK_200MHz : in  std_logic;
        button     : in  std_logic;
        reset      : in  std_logic;
        LED        : out std_logic_vector(3 downto 0) --array of LED's
    );

end button_press;

architecture Behavioral of button_press is
    signal CLK_1Hz : std_logic;         --input clock (think 200 MHz)
    signal counter : std_logic_vector(26 downto 0); --counter to turn 200 MHz clock to 1 Hz
    signal binary  : std_logic_vector(3 downto 0); --binary vector thats mapped to LED's
begin
    -----Create 1 Hz clock signal from 200 MHz system clock-------
    prescaler : process(CLK_200MHz)
    begin
        if rising_edge(CLK_200MHz) then
            if (counter < 2500000) then --possibly change to number in binary
                counter <= counter + 1;
            else
                CLK_1Hz <= not CLK_1Hz; --toggle 1 Hz clock
                counter <= (others => '0'); --reset counter to 0
            end if;
        end if;
    end process;
    ------ Increment binary number when on rising clock edge when button pressed -------
    binary_proc : process(CLK_1Hz, button, reset) --include all inputs on sensitivity list
    begin
        if rising_edge(CLK_1Hz) and button = '1' then
            binary <= binary + 1;
        end if;
        if reset = '1' then
            binary <= (others => '0');
        end if;
    end process;

    LED <= binary;                      --map binary number to LED's

end Behavioral;

推荐答案

问题是，重置是以<$为条件的c $ c> not（rising_edge（CLK_1Hz）和button ='1'），Xilinx XST工具无法弄清楚如何将其映射到FPGA硬件。

The problem is, that reset is conditional to not (rising_edge(CLK_1Hz) and button = '1'), and the Xilinx XST tool can't figure out how to map this to FPGA hardware.

VHDL是硬件描述语言（VHDL的HDL部分），所以不要把它想象成编写另一个程序（例如在C或Python中），而是将其视为描述电路。

VHDL is a Hardware Description Language (HDL part of VHDL), so don't think of it like writing another program (e.g. as in C or Python), but think of it as describing a circuit.

将VHDL代码转换为硬件是一项复杂的任务，Xilinx希望设计人员使用一些模式，如XST硬件描述语言
（HDL）中所述 Xilinx XST用户指南中的编码技术。第一个代码部分不遵循任何这些模式，XST无法将其转换为硬件，因此警告。

Converting VHDL code to hardware is a complicated task, and Xilinx expects the designer to use some patterns, as described in the "XST Hardware Description Language (HDL) Coding Techniques" of the Xilinx XST User Guide. The first code part does not follow any of these patterns, and XST fails to convert this to hardware, thus the warning.

根据编码风格，编写方式它将是：

As per that coding style, the way to write it would be:

process(CLK_1Hz, reset) is  -- Don't include button, since sync. signal
begin
  if reset = '1' then
    binary <= (others => '0');
  elsif rising_edge(CLK_1Hz) then
    if button = '1' then
      binary <= binary + 1;
    end if;
  end if;
end process;

Btw。考虑不要将额外的时钟设为 CLK_1Hz ，而是改为使用增量使能信号，因为每个时钟都需要特殊处理和资源。

Btw. consider not making an extra clock as CLK_1Hz, but make an increment enable signal instead, since every clock requires special handling and resources.

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