Ice Lake的48KiB L1数据缓存的索引如何工作? [英] How does the indexing of the Ice Lake's 48KiB L1 data cache work?

问题描述

英特尔手动优化(2019年9月修订)显示了针对Ice Lake微体系结构的48 KiB 8路关联L1数据缓存.

The Intel manual optimization (revision September 2019) shows a 48 KiB 8-way associative L1 data cache for the Ice Lake microarchitecture.

^{1 软件可见的延迟/带宽将根据访问模式和其他因素而变化.}

^{1 Software-visible latency/bandwidth will vary depending on access patterns and other factors.}

这让我感到困惑，因为:

This baffled me because:

• 有96组(48 KiB/64/8)，不是2的幂.
• 集合的索引位和字节偏移的索引位加起来超过12位，这使得 cheap-PIPT -as-VIPT-技巧不适用于4KiB页面.

• There are 96 sets (48 KiB / 64 / 8), which is not a power of two.
• The indexing bits of a set and the indexing bits of the byte offset add to more than 12 bits, this makes the cheap-PIPT-as-VIPT-trick not available for 4KiB pages.

总而言之，似乎缓存的处理成本更高，但延迟仅略有增加(如果确实如此，则取决于Intel确切地表示该数字的含义).

All in all, it seems that the cache is more expensive to handle but the latency increased only slightly (if it did at all, depending on what Intel means exactly with that number).

凭借一些创造力，我仍然可以想象出一种快速索引96组数据的方法，但是第二点对我来说似乎是一个重要的突破性变化.

With a bit of creativity, I can still imagine a fast way to index 96 sets but point two seems an important breaking change to me.

我想念什么?

推荐答案

优化手册是错误的.

根据CPUID指令，关联性为12(在Core i5-1035G1上).另请参见 uops.info/cache.html 和

According to the CPUID instruction, the associativity is 12 (on a Core i5-1035G1). See also uops.info/cache.html and en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client).

这意味着有64套，与以前的微体系结构相同.

This means that there are 64 sets, which is the same as in previous microarchitectures.

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