ARM11转换后备缓冲器（TLB）的用法？ [英] ARM11 Translation Lookaside Buffer (TLB) usage?

问题描述

有一个体面的指南，说明如何使用TLB（翻译后援缓冲器的）上的 ARM1176JZF-S 核心表？

说完看了看的是ARM平台的技术文档我仍然不知道一个TLB是什么，或者什么样子。据我了解，每一个TLB项的虚拟页面映射到物理页，允许重映射和控制内存的权限。

除此之外，我对如何使用它们丝毫没有线索。

• 没有一个TLB项有什么结构？如何创建新的项目？


• 如何处理虚拟机的上下文切换用户空间线程？我如何确保这些线程只能访问分配给他们的父进程特定页面（执行内存保护的）？难道我救TLB状态为每个上下文？


• 为什么有两个TLB的？我可以使用什么MicroTLB因为如果它只能有10个条目？当然，我需要超过10个。


• 它说，主TLB的部分之一就是八素的全关联数组，这是可锁定。那是什么？难道我只能得到有8项主TLB？

谢谢你在前进。我来，如果有人提供了什么样的TLB是一个解释是真的很高兴。我目前工作的一个内存映射为我的内核，我已经pretty多少进入了死胡同。

解决方案

有关ARM1176JZF-S的技术参考手册似乎是DDI 0301该文件包含所有特定ARM内核的具体细节。

我仍然不知道一个TLB是什么，或者什么样子。据我了解，每一个TLB项的虚拟页面映射到物理页，允许重新映射和控制内存的权限。

一个TLB是页表的缓存。某些处理器允许TLB的直接访问，而寂寂页表没有（例如：MIPS），而其他人知道的页表，并在内部使用TLB的程序员大多没有看到（例如：86）。在这种情况下，TLB由硬件管理，系统程序员仅需要关心使寄存器指向页表的TTB（转换表碱），以及无效TLB中apropriate地方

做了TLB项有什么结构？如何创建新的项目？

由硬件完成。在一个TLB缺失时，MMU从那里走页表并填充TLB。

如何处理虚拟机的上下文切换用户空间线程？

有些平台有TLB的，简单地映射到物理地址的虚拟地址（例如：86）。在这些平台上，你需要做的每一个上下文切换在一个完整的TLB冲洗。其它平台（MIPS，这个特定的ARM内核）地图（ASID，虚拟地址对）的物理地址。一个ASID是一个特定应用标识符，即：对一个过程的标识符。该MMU使用一个寄存器知道哪些ASID使用（我认为这是在这种情况下，上下文ID寄存器）。由于有可能比ASIDs多个进程，有时您可能需要回收的ASID（其分配给不同的过程），并做了刷新TLB（这是什么的Invalidate TLB ASID通过操作对）。

为什么有两个TLB的？我可以使用什么MicroTLB因为如果它只能有10个条目？当然，我需要超过10个。

这正是你有小的独立的一级缓存1指令和数据一样的道理。由于他们是缓存，你不这样做的需求的超过10（虽然有更多可以提高性能）。

它说，主TLB的部分之一就是八素的全关联数组，这是可锁定。那是什么？难道我只能得到有8项主TLB？

有些内存页面（例如：内核的某些部分）都经常访问。这是有道理的锁定他们，所以他们没有得到揭去TLB的。此外，在实时系统中，一个TLB错过或高速缓存未命中可能会出台一些不必要的未predictability。所以，有锁定若干TLB条目的选项。主TLB有更多的条目，但只有8是上锁的。

Is there a decent guide explaining how to use the TLB (Translation Lookaside Buffers) tables on an ARM1176JZF-S core?

Having looked over the technical documentation for the that ARM platform I still have no clue what a TLB is or what it looks like. As far as I understand, each TLB entry maps a virtual page to a physical page, allowing remapping and controlling memory permissions.

Apart from that, I have absolutely no clue on how to use them.

• What structure does a TLB entry have? How do I create new entries?
• How do I handle VM in context switches for user-space threads? How do I ensure that those threads can only access specific pages assigned to their parent processes (enforce memory protection)? Do I save the TLB state for each context?
• Why are there two TLBs? What can I use the MicroTLB for if it can only have 10 entries? Surely, I need more than 10.
• It says that one of the parts of the main TLB is "a fully-associative array of eight elements, that is lockable". What is that? Do I only get to have 8 entries for the Main TLB?

Thank you in advance. I'll be really glad if someone provides an explanation of what TLBs are. I'm currently working on a memory mapper for my kernel, and I've pretty much hit a dead end.

解决方案

The technical reference manual for ARM1176JZF-S appears to be DDI 0301. That document contains all the specific details for that specific ARM core.

I still have no clue what a TLB is or what it looks like. As far as I understand, each TLB entry maps a virtual page to a physical page, allowing remapping and controlling memory permissions.

A TLB is a cache of the page table. Some processors allow direct access to the TLB, while knowing nothing about page tables (e.g: MIPS), while others know about page tables, and internally use TLBs that the programmer mostly doesn't see (e.g: x86). In this case, the TLB is managed by hardware, and the system programmer only has to care to make the TTB (Translation Table Base) registers point to the page table, and invalidate the TLB in apropriate places.

What structure does a TLB entry have? How do I create new entries?

Done by hardware. On a TLB miss, the MMU walks the page table and fills the TLB from there.

How do I handle VM in context switches for user-space threads?

Some platforms have TLBs that simply map virtual addresses to physical addresses (e.g: x86). On these platforms, you have to do a full TLB flush on each context switch. Other platforms (MIPS, this specific ARM core) map (ASID, virtual address) pairs to physical addresses. An ASID is an Application-Specific Identifier, i.e: an identifier for a process. The MMU uses a register to know which ASID to use (I think it's the Context ID register in this case). Since there may be more processes than ASIDs, occasionally you may need to recycle an ASID (assigning it to a different process) and do a TLB flush (that's what the Invalidate TLB by ASID operation is for).

Why are there two TLBs? What can I use the MicroTLB for if it can only have 10 entries? Surely, I need more than 10.

This is exactly for the same reason you have small separate level-1 caches for instructions and data. Since they are caches, you don't need more than 10 (though having more could improve performance).

It says that one of the parts of the main TLB is "a fully-associative array of eight elements, that is lockable". What is that? Do I only get to have 8 entries for the Main TLB?

Some memory pages (e.g: some portions of the kernel) are accessed very often. It makes sense to lock them, so they don't get thrown off of the TLB. Also, on realtime systems, a TLB miss or a cache miss may introduce some unwanted unpredictability. So, there is an option to lock a number of TLB entries. The main TLB has more entries, but only those 8 are lockable.

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