ARM11 转换后备缓冲区 (TLB) 用法? [英] ARM11 Translation Lookaside Buffer (TLB) usage?

问题描述

是否有解释如何在 ARM1176JZF-S 内核上使用 TLB(Translation Lookaside Buffers)表的体面指南?

Is there a decent guide explaining how to use the TLB (Translation Lookaside Buffers) tables on an ARM1176JZF-S core?

查看了该 ARM 平台的技术文档后，我仍然不知道 TLB 是什么或它是什么样子.据我了解，每个 TLB 条目将一个虚拟页面映射到一个物理页面，从而允许重新映射和控制内存权限.

Having looked over the technical documentation for the that ARM platform I still have no clue what a TLB is or what it looks like. As far as I understand, each TLB entry maps a virtual page to a physical page, allowing remapping and controlling memory permissions.

除此之外，我完全不知道如何使用它们.

Apart from that, I have absolutely no clue on how to use them.

• TLB 条目具有什么结构?如何创建新条目?
• 如何在用户空间线程的上下文切换中处理 VM?我如何确保这些线程只能访问分配给其父进程的特定页面(强制内存保护)?我是否为每个上下文保存 TLB 状态?
• 为什么有两个 TLB?如果 MicroTLB 只能有 10 个条目，我可以用它做什么?当然，我需要 10 个以上.
• 它说主 TLB 的一个部分是一个由 8 个元素组成的完全关联的数组，它是可锁定的".那是什么?主 TLB 只能有 8 个条目吗?

• What structure does a TLB entry have? How do I create new entries?
• How do I handle VM in context switches for user-space threads? How do I ensure that those threads can only access specific pages assigned to their parent processes (enforce memory protection)? Do I save the TLB state for each context?
• Why are there two TLBs? What can I use the MicroTLB for if it can only have 10 entries? Surely, I need more than 10.
• It says that one of the parts of the main TLB is "a fully-associative array of eight elements, that is lockable". What is that? Do I only get to have 8 entries for the Main TLB?

在此先感谢您.如果有人解释什么是 TLB，我会非常高兴.我目前正在为我的内核开发内存映射器，但我几乎陷入了死胡同.

Thank you in advance. I'll be really glad if someone provides an explanation of what TLBs are. I'm currently working on a memory mapper for my kernel, and I've pretty much hit a dead end.

推荐答案

ARM1176JZF-S 的技术参考手册似乎是 DDI 0301.该文档包含该特定 ARM 内核的所有具体细节.

The technical reference manual for ARM1176JZF-S appears to be DDI 0301. That document contains all the specific details for that specific ARM core.

我仍然不知道什么是 TLB 或者它是什么样子.据我了解，每个 TLB 条目将一个虚拟页面映射到一个物理页面，从而允许重新映射和控制内存权限.

I still have no clue what a TLB is or what it looks like. As far as I understand, each TLB entry maps a virtual page to a physical page, allowing remapping and controlling memory permissions.

TLB 是页表的缓存.一些处理器允许直接访问 TLB，但对页表一无所知(例如:MIPS)，而其他处理器知道页表，并且在内部使用程序员通常看不到的 TLB(例如:x86).在这种情况下，TLB 是由硬件管理的，系统程序员只需要让 TTB(Translation Table Base)寄存器指向页表，并在适当的地方使 TLB 失效.

A TLB is a cache of the page table. Some processors allow direct access to the TLB, while knowing nothing about page tables (e.g: MIPS), while others know about page tables, and internally use TLBs that the programmer mostly doesn't see (e.g: x86). In this case, the TLB is managed by hardware, and the system programmer only has to care to make the TTB (Translation Table Base) registers point to the page table, and invalidate the TLB in apropriate places.

TLB 条目有什么结构?如何创建新条目?

What structure does a TLB entry have? How do I create new entries?

由硬件完成.在 TLB 未命中时，MMU 遍历页表并从那里填充 TLB.

Done by hardware. On a TLB miss, the MMU walks the page table and fills the TLB from there.

如何在用户空间线程的上下文切换中处理 VM?

How do I handle VM in context switches for user-space threads?

某些平台具有将虚拟地址简单地映射到物理地址的 TLB(例如:x86).在这些平台上，您必须在每次上下文切换时执行完整的 TLB 刷新.其他平台(MIPS，这个特定的 ARM 内核)将(ASID，虚拟地址)对映射到物理地址.ASID 是特定于应用程序的标识符，即:进程的标识符.MMU 使用一个寄存器来知道要使用哪个 ASID(我认为在这种情况下是上下文 ID 寄存器).由于进程可能比 ASID 多，因此有时您可能需要回收一个 ASID(将其分配给不同的进程)并执行 TLB 刷新(这就是 Invalidate TLB by ASID 操作的目的).

Some platforms have TLBs that simply map virtual addresses to physical addresses (e.g: x86). On these platforms, you have to do a full TLB flush on each context switch. Other platforms (MIPS, this specific ARM core) map (ASID, virtual address) pairs to physical addresses. An ASID is an Application-Specific Identifier, i.e: an identifier for a process. The MMU uses a register to know which ASID to use (I think it's the Context ID register in this case). Since there may be more processes than ASIDs, occasionally you may need to recycle an ASID (assigning it to a different process) and do a TLB flush (that's what the Invalidate TLB by ASID operation is for).

为什么有两个 TLB?如果 MicroTLB 只能有 10 个条目，我可以用它做什么?当然，我需要 10 个以上.

Why are there two TLBs? What can I use the MicroTLB for if it can only have 10 entries? Surely, I need more than 10.

这与您拥有用于指令和数据的小型独立 1 级缓存的原因完全相同.由于它们是缓存，因此您不需要超过 10 个(尽管更多可以提高性能).

This is exactly for the same reason you have small separate level-1 caches for instructions and data. Since they are caches, you don't need more than 10 (though having more could improve performance).

它说主 TLB 的一个部分是一个由 8 个元素组成的完全关联的数组，它是可锁定的".那是什么?主 TLB 只能有 8 个条目吗?

It says that one of the parts of the main TLB is "a fully-associative array of eight elements, that is lockable". What is that? Do I only get to have 8 entries for the Main TLB?

某些内存页面(例如:内核的某些部分)会经常被访问.锁定它们是有意义的，这样它们就不会被从 TLB 中抛出.此外，在实时系统上，TLB 未命中或缓存未命中可能会引入一些不必要的不​​可预测性.因此，可以选择锁定多个 TLB 条目.主 TLB 有更多条目，但只有 8 个是可锁定的.

Some memory pages (e.g: some portions of the kernel) are accessed very often. It makes sense to lock them, so they don't get thrown off of the TLB. Also, on realtime systems, a TLB miss or a cache miss may introduce some unwanted unpredictability. So, there is an option to lock a number of TLB entries. The main TLB has more entries, but only those 8 are lockable.

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