如何在 Verilog 中编写具有可变端口数的模块 [英] How to write a module with variable number of ports in Verilog

问题描述

我想编写一个具有可变数量输入的模块，即根据某些参数，结果将是:

I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be:

module my_module #(LENGTH)(
    input clk,
    input rst_n,
    input [LENGTH-1:0] data_1
);
//...
endmodule

或

module my_module #(LENGTH)(
    input clk,
    input rst_n,
    input [LENGTH-1:0] data_1,
    input [LENGTH-1:0] data_2,
    input [LENGTH-1:0] data_3
);
//...
endmodule

是否可以在 Verilog 或 Systemverilog 中执行此操作，或者我是否必须编写脚本，例如在 Python 中，以便为具有固定数量输入的特定模块生成代码?(可能超过 1000 个输入)

Would it be possible to do this in Verilog or Systemverilog or would I have to write a script, let's say in Python, in order to generate the code for a specific module with fixed number of inputs? (it might be more than 1000 inputs)

推荐答案

SystemVerilog 中没有可变数量的端口，但您可以使用参数化数组的端口.

There are no variable number of ports in SystemVerilog, but you could use a port that is a parameterized array.

module my_module #(int LENGTH, DEPTH)(
    input clk,
    input rst_n,
    input [LENGTH-1:0] data[DEPTH]
);
//...
endmodule

否则，您将需要使用脚本来生成代码.

Otherwise, you would need to use a script to generate the code.

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