在网表 VHDL 中初始化内存 [英] Initializing memory in netlist VHDL

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问题描述

使用 Synopsis DC 工具合成处理器代码后

After synthesizing a processor code using Synopsis DC tool

现在我想使用 .mem 文件初始化包含在此设计中的 2 个组件中的 2 个 ram

Now I want to initialize 2 rams included in 2 components in this design using .mem files

我如何使用我拥有的网表文件来实现这一点 - 合成的输出 - 因为我想通过在处理器上再次测试相同的代码来测试合成是否正确

how do I achieve that using the netlist file I have - the output of synthesizing - because I want to test if synthesizing was done right by testing the same code again on processor

只需将 .mem 文件加载到这些 ram 中然后对其进行测试,无需在合成之前就更容易了

It was easier without before synthesizing just by loading .mem files into those rams and then testing it

任何帮助

推荐答案

不要费心加载 .mem 文件;只需直接在 VHDL 中初始化存储器.

Don't bother loading .mem files; just initialise the memories directly in VHDL.

最简单的方法 - 如果它们是 ROM - 是将它们声明为常量数组.如果此声明位于单独的包中,您可以轻松地从编译器或汇编器创建的 hex 文件编写其创建脚本.

The simplest method - if they are ROMs - is to declare them as constant arrays. If this declaration is in a separate package you can easily script its creation from a hex file created by a compiler or assembler.

这是一个让您入门的示例

Here is an example to get you started

package Memories is

type Address is natural range 0 to 2**8 - 1;
type Byte is std_logic_vector(7 downto 0);

type Memory is array(Address) of Byte;

-- Positional association is convenient if you are filling the whole memory
-- constant ROM1 : Memory := (X"00", X"11", X"22", and so on);
-- I'm not going to type out the lot!

-- Named association is better for a simple test program
constant ROM2 : memory := (
   0     => X"C3",
   1     => X"38",
   2     => X"00",
  16#38# => X"C3",
  16#39# => X"00",
  16#3A# => X"00",
  others => X"FF"
);

end Memories;

如果它们是 RAM,您可以从同一个常量数组调用初始化它们.

If they are RAMs, you can call initialise them from the same constant array.

use Memories.all;
constant ROM : Memory := ROM2;
signal   RAM : Memory := ROM2;

即使是我至少在过去五年中使用过的最原始的综合工具也能正确处理这些结构,所以如果 DC 不能做同样的事情,我会感到非常惊讶.

These constructs are correctly handled by even the most primitive synthesis tools I have used in the last five years at least, so I would be very surprised if DC can't do the same.

初始数据必须由综合工具保存并以某种形式出现在网表中.如果你能理解那个表格,你可以在必要时修改数据,但更新源和重新合成可能更容易.

That initial data must be preserved by the synthesis tool and appear in some form in the netlist. If you can understand that form, you can modify the data if necessary, but it is probably easier to update the source and re-synthesise.

这篇关于在网表 VHDL 中初始化内存的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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