补码比较器的 Verilog 构造 [英] Verilog Construction of Two's Complement Comparator

问题描述

我正在尝试为两个 4 位二进制补码的比较器编写一些简单的 verilog 代码.我有两个 4 位输入(A[3:0]、B[3:0])和 3 个输出(AeqB、AgtB、AltB)来显示 A 和 B 是否相等，如果 A 大于 B，或者A 小于 B.还有第三个输入叫做 sign，如果 0 表示数字是无符号的，如果是 1 则表示数字是有符号的.

I am trying to write some simple verilog code for a comparator of two 4 bit two's complement numbers. I have two 4-bit inputs (A[3:0], B[3:0]), and 3 outputs (AeqB, AgtB, AltB) to show if A and B are equal, if A is greater than B, or A is less than B. There is also a third input named sign, which if 0 means that the numbers are unsigned, and if 1, the numbers are signed.

所以我知道可以通过相减来比较两个带符号的二进制补码，但是我无法在我的设计中正常工作.这是我尝试过的:

So i know that two signed two's complement numbers can be compared by subtracting them, but i cannot get that to work properly in my design. Here is what i have tried:

if(sign==0)
 begin

    if(({sign,A}-{sign,B})==0)
        AeqB = 1;
    else if(({sign,A}-{sign,B}) > 0)
        AgtB = 1;
    else if (({sign,A}-{sign,B}) < 0
        AltB = 1;
end

这似乎应该有效.我将符号位连接到 4 位数字的前面，将它们相减，然后检查它们是否大于或等于 0.如果 A-B<0，则 B 小于 A，因为它们都是负数.

It seems as though this should work. I concatenate the sign bit to the front of the 4 bit numbers, subtract them, and then check to see if they are greater than or equal to zero. If A-B<0, then B is less than A because they are both negative numbers.

然而，当我模拟这个设计时，每当 A=B 时它都是正确的，但在所有其他情况下都显示 AgtB，而不是 AltB.

However when i simulate this design, it is correct whenever A=B, but shows AgtB in every other case, never AltB.

对我做错了什么有任何想法吗?

Any ideas on what i am doing wrong?

推荐答案

我不确定你在用 {sign,A} 做什么.当它们具有签名格式时，这将强制数字为负数.除非符号迫使它们为负?

I am not sure what you are doing with {sign,A}. This would force the numbers to be negative when they have a signed format. Unless sign forces them to be negative?

您可以定义要有符号的输入或强制进行有符号比较，并在无符号情况下填充 msb 以共享硬件，您所暗示的是三个并行减法器.Synthesis 可能会做得很好并且可以共享硬件，但您每次都必须检查它是否提供了您想要的东西.

you could define inputs to be signed or force a signed comparison, and 0 pad the msb in the unsigned case to share hardware, what you have implied is three subtractors in parallel. Synthesis might do a great job and share the hardware but you would have to check each time that it has given you what you want.

if (sign) begin
   A_i = {A[3], A};
   B_i = {B[3], B};
end
else begin
   A_i = {1'b0, A};
   B_i = {1'b0, B};
end

AgtB = $signed(A_i) > $signed(B_i) ;
AltB = ~AgtB ;

当加减数时，结果位增长是最大位宽输入+1.对于无符号 0 填充和中断结果为无符号.对于有符号数字，通过重复 MSB 进行符号扩展.

When adding subtracting numbers the result the bit growth is the largest bit width input +1. for unsigned 0 pad and interrupt result as unsigned. For signed numbers, sign extend by repeating the MSB.

为了帮助理解 2 的补码，我提供了一些 4 位无符号算术示例.

To help with the understanding of 2's complement I have included some 4 bit examples of sign unsigned arithmetic.

无符号算术:

   3 : (0)0011 
 + 1 : (0)0001
 = 4 :  0 0100    

大型无符号算术:

  15 :  (0)1111 //Zero pad for correct bitwidths
 + 1 :  (0)0001
 =16 :   1 0000

大签名(溢出):
在结果上，不同的 (01) MSB 表示溢出以截断回 4 位

Large Signed (Overflow):
On the result different (01) MSBs indicate overflow for truncation back down to 4 bits

   7 : (0)0111
  +1 : (0)0001
  =8 :  0 1000 bits

减法:

   7 : (0)0111
  -1 : (1)1111 //(twos complement of 1)
  // Sum the bits as you did for unsigned
  =6 :  0 0110  

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