如何在Verilog中初始化推断的Block RAM(BRAM)的内容 [英] How to initialize contents of inferred Block RAM (BRAM) in Verilog

问题描述

我无法在Verilog中初始化推断的ram的内容. ram的代码如下:

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below:

module ram(
        input clock, // System clock
        input we, // When high RAM sets data in input lines to given address
        input [13:0] data_in, // Data lines to write to memory
        input [10:0] addr_in, // Address lines for saving data to memory
        input [10:0] addr_out, // Address for reading from ram
        output reg data_out // Data out
);

reg [13:0] ram[2047:0];

// Initialize RAM from file
// WHAT SHOULD GO HERE?

always @(posedge clock) begin
    // Save data to RAM
    if (we) begin
        ram[addr_in] <= data_in;
    end

    // Place data from RAM
    data_out <= ram[addr_out];
end        
endmodule

我遇到了$ readmemh命令.但是，有关此文件的文档似乎很少.我应该如何格式化包含数据的文件?另外，在实例化此模块时如何传递文件作为参数，以便可以从不同文件加载该模块的不同实例?

I have run into the command $readmemh. However, documentation for it seems sparse. How should I format the file that contains the data? Also, how can I pass the file as argument when instantiating this module so that I can have different instances of this module load from different files?

我希望初始化后的内容可用于仿真和实际实现.这样FPGA就可以在RAM中使用此内容进行引导.

I want the initialized content to be available for both simulation and actual implementation. So that the FPGA already boots with this content in RAM.

我正在使用Vivado 2015.4对Kintex xc7k70 FPGA进行编程.

I am using Vivado 2015.4 to program a Kintex xc7k70 FPGA.

推荐答案

您应该在初始块内使用$readmemh是正确的.为了使模块的不同实例可以具有不同的初始化文件，应使用如下参数:

You are correct that you should use $readmemh inside an initial block. In order to make it so different instances of the module can have different initialization files, you should use a parameter like so:

parameter MEM_INIT_FILE = "";
...
initial begin
  if (MEM_INIT_FILE != "") begin
    $readmemh(MEM_INIT_FILE, ram);
  end
end

该格式在IEEE1800-2012规范的第21.4节中进行了描述；通常，文件只是一串包含正确位长的十六进制数字的行，如下所示:

The format is described in Section 21.4 of the IEEE1800-2012 specification; typically the file is just a bunch of lines containing hex numbers of the correct bit-length, like so:

0001
1234
3FFF
1B34
...

请注意，没有前缀"0x"，并且每一行代表一个相邻地址(或任何分隔的空格).在上面的示例中，$readmemh将14'h0001放入ram[0]，14'h1234放入ram[1]，14'h3FFF放入ram[2]，依此类推.您还可以使用//或/* */在十六进制文件中包含注释.最后，您可以使用@符号为以下数字指定地址，就像这样:

Note that there is no "0x" prefix and each line represents an adjacent address (or any separating whitespace). In the example above, $readmemh would put 14'h0001 into ram[0], 14'h1234 into ram[1], 14'h3FFF into ram[2] and so on. You can also include comments in the hex file using // or /* */. Finally, you can use the @ symbol to designate an address for the following numbers to be located at, like so:

@0002
0101
0A0A
...

在上面的文件中，ram[0]和ram[1]将未初始化，而ram[2]将得到14'h0101.这些都是十六进制文件格式的主要构造，尽管您也可以像使用其他Verilog编号一样使用_，x和z，并且在上述部分中可以找到更多规则.

In the above file, ram[0] and ram[1] would be uninitialized and ram[2] would get 14'h0101. Those are all the major constructs of the hex file format, though you can also use _, x and z as you would in other Verilog numbers and theres a few more rules you can read in the section sited above.

这篇关于如何在Verilog中初始化推断的Block RAM(BRAM)的内容的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！