实数计算，Verilog HDL [英] Calculations with Real Numbers, Verilog HDL

问题描述

我注意到 Verilog 将我的实数结果四舍五入为整数结果.例如，当我查看模拟器时，它显示 17/2 的结果为 9.我该怎么办?无论如何定义类似的东西: output real reg [11:0] output_value ?还是必须通过模拟器设置来完成?

I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it shows the result of 17/2 as 9. What should I do? Is there anyway to define something like a: output real reg [11:0] output_value ? Or is it something that has to be done by simulator settings?

仅模拟(无合成).示例:
x 定义为有符号输入，output_value 定义为输出 reg.

Simulation only (no synthesis). Example:
x defined as a signed input and output_value defined as output reg.

output_value = ((x >>> 1) + x) + 5; 

如果 x=+1 那么输出值必须是:13/2=6.5.

If x=+1 then output value has to be: 13/2=6.5.

但是，当我模拟时，我看到 output_value = 6.

However when I simulate I see output_value = 6.

推荐答案

代码会有所帮助，但我怀疑您根本没有划分实数.17 和 2 是整数，所以像这样的简单语句将进行整数除法.

Code would help, but I suspect your not dividing reals at all. 17 and 2 are integers, and so a simple statement like that will do integer division.

17   / 2   = 8 (not 9, always rounds towards 0)
17.0 / 2.0 = 8.5

第二种情况

output_value = ((x >>> 1) + x) + 5

如果 x 为 1，则 x >>>1 是 0，而不是 0.5，因为你刚刚离开了单词的底部.

If x is 1, x >>> 1 is 0, not 0.5 because you've just gone off the bottom of the word.

output_value = ((1 >>> 1) + 1) + 5 = 0 + 1 + 5 = 6

这里 verilog 没有什么特别之处.大多数语言都是如此.

There's nothing special about verilog here. This is true for the majority of languages.

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