VHDL FSM多驱动网Q连接到常量驱动，其他驱动被忽略，我的代码有什么问题? [英] VHDL FSM multi-driven net Q is connected to constant driver, other driver is ignored, what's wrong with my code?

问题描述

Alyssa P. Hacker 有一只蜗牛从纸带上爬下来上面有 1 和 0.蜗牛每当最后两个微笑它爬过的数字是01. 设计 Moore 和 Mealy蜗牛大脑的 FSM.

Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs of the snail’s brain.

代码如下

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity simpfsm is
Port ( A : in STD_LOGIC;
       clk : in STD_LOGIC;
       r   : in STD_LOGIC;
       Y : out STD_LOGIC);
end simpfsm;


architecture Behavioral of simpfsm is
type state_type is (SA,SB,SC);
signal state,next_state:state_type;
begin
SYNC_PROC:process(clk)
begin
if(clk'event and clk='1') then
if(r='1') then
next_state <= SA; -- removed trailing grave accent
else
state <= next_state;
end if;
end if;
end process;

OUTPUT_DECODE:process(state)
begin
case (state) is
when SA =>
Y <= '0';
when SB =>
Y <= '0';
when SC =>
Y <= '1';
when others =>
Y <= '0';
end case;
end process;

NEXT_STATE_DECODE:process(state,A)
begin
next_state <= state;
case (state) is

    when SA =>
        if(A='0') then
            next_state <= SB;
        end if;

    when SB =>
        if(A='1') then
            next_state <= SC;
        end if;

    when SC =>
        if(A='0') then
            next_state <= SB;
        elsif(A='1') then
            next_state <= SA;
        end if;
    when others =>
        next_state <= SA;                       --"if not state then begin with SA"
end case;
end process;
end Behavioral;  -- removed trailing grave accent

错误是 [XSIM 43-3249] 文件 D:/Users/93443/project_4/project_4.srcs/sources_1/new/A_11_fsm.vhd，第 22 行.未解析的信号next_state"被多重驱动.

The error is [XSIM 43-3249] File D:/Users/93443/project_4/project_4.srcs/sources_1/new/A_11_fsm.vhd, line 22. Unresolved signal "next_state" is multiply driven.

推荐答案

state_type 不是解析的子类型.在细化过程中识别后，在模型执行之前的加载过程中检测到多个驱动程序.

state_type is not a resolved subtype. Multiple drivers are detected during loading prior to model execution after being identified during elaboration.

IEEE 标准 1076-2008

IEEE Std 1076-2008

14.5 声明部分的细化
14.5.5 其他并发语句

14.5 Elaboration of a statement part
14.5.5 Other concurrent statements

所有其他并发语句要么是进程语句，要么是具有等效进程语句的语句.流程语句的详细说明如下:

All other concurrent statements are either process statements or are statements for which there is an equivalent process statement. Elaboration of a process statement proceeds as follows:

a) 阐述了流程声明部分.
b) 确定了流程声明所需的驱动因素.

a) The process declarative part is elaborated.
b) The drivers required by the process statement are identified.

6.4.2.3 信号声明

6.4.2.3 Signal declarations

... 如果在详细描述之后，一个信号有多个来源并且它不是一个已解析的信号，那么这是一个错误....

... It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal. ...

进程 SYNC_PROC 和 NEXT_STATE_DECODE 中有 next_state 的驱动程序

There are drivers for next_state in processes SYNC_PROC and NEXT_STATE_DECODE

14.7 模型的执行
14.7.2 驱动程序

14.7 Execution of a model
14.7.2 Drivers

进程语句中的每个信号赋值语句都为某些标量信号定义了一组驱动程序.进程语句中的给定标量信号 S 有一个驱动程序，前提是该进程语句中至少有一个信号赋值语句，并且该信号赋值语句的目标信号的最长静态前缀表示 S 或表示一个S 是其子元素的复合信号.据说每个这样的信号赋值语句都与该驱动程序相关联.信号赋值语句的执行仅影响关联的驱动程序.

Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals. There is a single driver for a given scalar signal S in a process statement, provided that there is at least one signal assignment statement in that process statement and that the longest static prefix of the target signal of that signal assignment statement denotes S or denotes a composite signal of which S is a subelement. Each such signal assignment statement is said to be associated with that driver. Execution of a signal assignment statement affects only the associated driver(s).

state_type 枚举类型，标量类型:

state_type an enumerated type and is a scalar type:

5.2 标量类型
5.2.1 概述

5.2 Scalar types
5.2.1 General

标量类型包括枚举类型、整数类型、物理类型和浮点类型....

Scalar types consist of enumeration types, integer types, physical types, and floating-point types. ...

解决方案似乎是重置 SYNC_PROC 中的 state 而不是 next_state.

The solution would appear to be to reset state in SYNC_PROC instead of next_state.

如果您删除两个无关的重音符('`'，15.2 字符集)，您的代码将是一个最小、完整和可验证的示例 尽管 Tricky 表示怀疑.我从您的代码示例中删除了它们，之后您的代码会根据对处理 SYNC_PROC 的更改进行分析和详细说明:

If you remove the two extraneous grave accents ('`', 15.2 Character set) your code would be a Minimal, Complete, and Verifiable example despite Tricky's expression of suspicion. I removed them from your code example, after which your code analyzes and elaborates following the change to process SYNC_PROC:

if(r='1') then
state <= SA;  -- WAS next_state

(请注意，条件周围的括号(此处为 r='1')是多余的.在 VHDL 中，已知条件是具有 BOOLEAN 值的表达式.)

(Note the parentheses around a condition (here r='1') are redundant. In VHDL a condition is known to be an expression with a BOOLEAN value.)

如果您的模拟器允许使用顶级端口执行，它将报告多个驱动程序.对于那些不需要的模拟器，您需要一个测试台实例化 simpfsm:

If your simulator allows execution with top level ports it would report the multiple drivers. For those simulators that don't you'd require a testbench instantiating simpfsm:

14.2 详细设计层次结构

14.2 Elaboration of a design hierarchy

实现可以允许但不要求允许位于设计层次结构根部的设计实体具有泛型和端口.如果一个实现允许这些顶级接口对象，它可能会限制它们允许的形式(即，它们是否被允许是接口类型、子程序、包或对象)，并且在这种情况下接口对象，它们以实现定义的方式允许的类型和模式.

An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these top-level interface objects, it may restrict their allowed forms (that is, whether they are allowed to be interface types, subprograms, packages, or objects), and, in the case of interface objects, their allowed types and modes in an implementation-defined manner.

正如您可能收集到的那样，这代表了一个可移植性问题，用于在没有测试平台的情况下或依赖脚本驱动模拟器的交互来检测错误.该错误可以在信号分配目标更改之前使用 ghdl 进行演示:

As you might gather this represents a portability issue for detecting the error without a testbench or depending on an interactive of script driven simulator. The error can demonstrated with ghdl prior to the signal assignment target change:

ghdl -r simpfsm
对于信号:.simpfsm(behavioral).next_state
./simpfsm:error: 未解析信号的几个来源
./simpfsm:error: 细化过程中出错

ghdl -r simpfsm
for signal: .simpfsm(behavioral).next_state
./simpfsm:error: several sources for unresolved signal
./simpfsm:error: error during elaboration

在基于编译器的 VHDL 模拟器中将详细设计规范加载到内存中被推迟到程序"执行:

Loading an elaborated design specification into memory is deferred to 'program' execution in compiler based VHDL simulators:

14.2 设计层次结构的细化

14.2 Elaboration of a design hierarchy

设计层次的详细说明如下:

Elaboration of a design hierarchy is completed as follows:

——在详细说明过程语句(见 14.5.5)期间确定的驱动因素被创建.
— 由进程语句驱动的每个标量信号关联的默认值定义的初始事务插入到相应的驱动程序中.

— The drivers identified during elaboration of process statements (see 14.5.5) are created.
— The initial transaction defined by the default value associated with each scalar signal driven by a process statement is inserted into the corresponding driver.

next_state 和 state 都有 state_type'LEFT (SA) 的默认值.

next_state and state both have default values of state_type'LEFT (SA).

6.4.2.3 信号声明

6.4.2.3 Signal declarations

在没有显式默认表达式的情况下，对于标量子类型的信号或复合信号的每个标量子元素，假定隐式默认值，其中每个本身都是标量子类型的信号.标量子类型 T 的信号的隐式默认值定义为由 T'LEFT 给出的值.

In the absence of an explicit default expression, an implicit default value is assumed for a signal of a scalar subtype or for each scalar subelement of a composite signal, each of which is itself a signal of a scalar subtype. The implicit default value for a signal of a scalar subtype T is defined to be that given by T'LEFT.

这意味着在识别每个网络时，在细化的加载部分会检测到多个驱动程序:

And this implies detecting multiple drivers occurs during the loading portion of elaboration when each net is identified:

14.7.3.4 信号更新

14.7.3.4 Signal update

net 是驱动器、信号(包括端口和隐式信号)、转换函数和解析函数的集合，它们共同决定了网络上每个信号的有效值和驱动值.

A net is a collection of drivers, signals (including ports and implicit signals), conversion functions, and resolution functions that, taken together, determine the effective and driving values of every signal on the net.

我们看到在执行过程中(ghdl 的 -r 命令)的那部分细化(在此处加载):

We see in that part of elaboration (loading here) occurs during execution (ghdl's -r command):

14.2 详细设计层次结构

14.2 Elaboration of a design hierarchy

设计层次结构的细化创建了一系列由网络互连的过程；然后可以执行这些进程和网络的集合来模拟设计的行为.

The elaboration of a design hierarchy creates a collection of processes interconnected by nets; this collection of processes and nets can then be executed to simulate the behavior of the design.

Tricky 的怀疑是有一定道理的，重音会在分析过程中导致错误，而您提供的错误是在阐述过程中发生的.通过首先调查您报告的错误，可以假定它们是此处的转录错误.

Tricky's suspicion is somewhat valid, the grave accents would cause errors during analysis, while the error you provide occurs during elaboration. They can be assumed to be transcription errors here by investigating your reported error first.

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